Ultra low power vision processing chip enables miniature drones

June 20, 2018 // By Nick Flaherty
Ultra low power vision processing chip enables miniature drones
Researchers at MIT have shrunk the power consumption of a key chip for vision processing in small unmanned systems such as miniature drones.

The custom "Navion" chip consumes 24mW, down from 2W in the previous FPGA version, and handles real time video at a resolution of 752x480 at 171 frames per second as well as handling inertial measurements for positioning.

"I can imagine applying this chip to low-energy robotics, like flapping-wing vehicles the size of your fingernail, or lighter-than-air vehicles like weather balloons, that have to go for months on one battery," said Sertac Karaman, Associate Professor of Aeronautics and Astronautics and a member of the Laboratory for Information and Decision Systems and the Institute for Data, Systems, and Society at MIT. "Or imagine medical devices like a little pill you swallow, that can navigate in an intelligent way on very little battery so it doesn't overheat in your body. The chips we are building can help with all of these."

In their previous work, Vivienne Sze, associate professor in MIT's Department of Electrical Engineering and Computer Science (EECS) and Karaman tested out the algorithms in the FPGA implementation that was programmed at the desktop. However they estimate the power budget of small unmanned flying systems to be around 100mW.

To reduce the power consumption, the team used compressed data and optimised the data flow across the chip which is built in a 65nm CMOS process.

"Any of the images we would've temporarily stored on the chip, we actually compressed so it required less memory," said Sze, who is a member of the Research Laboratory of Electronics at MIT. The team also cut down on extraneous operations, such as the computation of zeros. "This allowed us to avoid having to process and store all those zeros, so we can cut out a lot of unnecessary storage and compute cycles, which reduces the chip size and power, and increases the processing speed of the chip," she said.

This reduced the on-chip memory from 2Mbytes to 0.8Mbytes to reduce the die size to 20mm2.

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