The €10m Mont Blanc 2020 project started last month and is looking at a number of areas that all impact on system-on-chip design. However the difference between the €10m for R&D and the €1bn being spent on buying four supercomputers and building the next generation one is striking.
The plan is to define a low-power System-on-Chip architecture targeting exascale systems and develop new critical IP building blocks (IPs) that will lead to the first generation processors. Those IP blocks will be shown in proof-of-concept demonstrations with real life applications and so will have to quite well developed.
It will also have to achieve low power consumption, and the project has identified three key challenges: vector length, network-on-chip (NoC) bandwidth and memory bandwidth. As a result the project is looking to develop a new on-die interconnect that can deliver enough bandwidth to the processing units with minimum energy consumption – NoC2.0 perhaps. Alongside that, the SoC architecture will need a high-bandwidth and low power memory system with enough capacity (terabytes) and bandwidth (Tbyte/s) for exascale applications. These are considerable challenges.
The consortium also includes French research and supercomputer provider CEA, Forschungszentrum Jülich, part of the German Helmholtz research group, French accelerator chip designer Kalray and Spanish processor architecture analysts SemiDynamics.
To improve the economic sustainability of the processor generations that will result from the work, the project includes the analysis of the requirements of other markets. The project’s strategy based on modular packaging would make it possible to create a family of SoCs targeting different markets, such as “embedded HPC” for autonomous driving.