Researchers at the Integrated Systems Laboratory (LSI) at EPFL in Switzerland have developed a method for reducing the power consumption of chips with a new way to map the logic flows in synthesis. Using a different set of logic functions for the gates allows designers to make their chips either smaller, faster or more energy efficient. Synopsys has acquired the rights to use the technology through a non-exclusive license agreement.
The low power technique developed by researcher Luca Amarù uses just two logic primitives: majority and inverter. These functions are displayed in majority-inverter graphs (MIGs). Initial studies indicated that his approach could cut the number of logic steps needed to execute a given task.
Later experiments confirmed this, finding that MIG optimization reduces the number of logic levels by 18% on average relative to standard programs. That frees up transistor capacity for other tasks so engineers could also use these gains to make their chips faster or their devices smaller.
“This new way of diagraming integrated circuits not only reduces the amount of power, computing time or space needed by nearly 20%, but also gives us a new logic paradigm that can be used in other applications, such as designing and improving FPGAs [field-programmable gate arrays] or searching and analyzing data sets,” said Mauro Lattuada, the technology-transfer manager at EPFL who arranged the license agreement.
Amarù, now a senior R&D manager at Synopsys, also developed a low power Boolean algebra for representing the logic functions, which resulted in additional efficiency gains for his system. Lab tests show the technique works particularly well with adders and dividers.