The CIO revealed that his company was engaged in small projects with a number of customers, to do mostly with miniaturized interconnects exploiting the high thermal and electrical conductivity of CNFs to boost traditional micro-bumps (with copper wetting and anchored onto CNF patches).
"You could find our IP in commercial applications within the next two to three years" he said.
"With this technology, we are not aiming at replacing Through Silicon Vias (TSVs) yet, but we'll solve the TSVs/interposer bottleneck. Copper micro-bumps don't scale too well", Kabir explained, "copper electro-migration impacts the lifetime reliability of silicon dies, and only CNF-based bumps will be able to scale down with future nodes".
In a whitepaper "Using carbon nanostructures as the assembly platform in semiconductor advanced packaging beyond Moore", the company mentions the use of selective electroplating, based on the conductive properties of CNFs to further reduce bump pitch without relying on micro solder balls. It sees a potential for 3D-shrinkage orders of magnitude (>10x-100x) compared to existing and well established bump/pillar technologies. This would allow bare dies to be stacked on each other or bonded to a substrate (interposer) or carrier (lead-frame) with much higher density interconnects.
An interesting ongoing development which could interest many OSATs doing Integrated Passive Devices (IPDs) for their customers is the SmolCACH (Capacitor on Chip) Smoltek is working on.