Semefab in the UK has produced samples of a new quantum tunnelling transistor and wafer process that could cut lead times, wafer area and process layers while increasing speed, reducing power and increasing gate density over CMOS.
The transistor architecture developed by startup Search For The Next (SFN) in Nottingham, UK, uses quantum tunnelling (above) rather than insulated gates. This architecture, called Bizen after the combination of bipolar and zener, allows logic to be produced in just eight layers on a standard CMOS process, rather than 20 to 30 for standard CMOS transistor designs. Test chips on a 1μm process produced by Semefab in Glenrothes, Scotland have cut the lead time from 15 weeks to three, and the die area is a third the size of a comparable CMOS device on the same process, said Allan James, CEO of Semefab, in an interview with eeNews Power
Quantum tunnelling is not new, as it is widely used in NOR flash memory chips. But with Bizen the technique has been applied to logic devices, proven by Semefab and extended to work with power devices.
“The integration of conventional lateral and vertical bipolar structures can, with careful modelling, be designed to incorporate Bizen without undue additional process complexity,” James told eeNews Power. “I was initially quite sceptical but having lived with the concept and seen early-stage results, it does indeed tick many of the boxes needed to disrupt the industry. It's not so much a question that CMOS is flawed - although CMOS is prone to latch up and ESD. CMOS is low power, has passed the test of time and is generally reliable. However, it is complex and when integrated with power even more so. Complexity means longer lead times and higher cost.”