The modules use a proprietary one wire interface as device synchronisation and chip communication was intentionally left out of the PMbus spec, which is currently at version 1.3. This was to encourage technology development among the suppliers, he says.
“You will see solutions that go both ways. We introduced a low cost simple PMbus 1.3 compliant DAC – it’s just a D to A converter that allows you to sum a current into a regulator but it complies with the high speed bus – that’s a very simple device, it doesn’t need to be configured and it’s low cost. You will see lower feature count, lower cost telemetry where instead of monitoring 20 parameters we monitor 4 – input current and voltage, and output current and voltage,” he said,
But there are also demands to support high performance multicore processors and FPGAs in datacentre infrastructure. This is leading to a new version of the specification.
“On the high end we see customers that need to power very complex, power hungry FPGAs or cores with precise control of the DC transient specifications and in addition they would like the system to be very adaptive with an almost infinite number of power states and for that they will need. They will need 1.3 with the high speed 50MHz SPI bus - this represents the other end of the spectrum that needs to communicate lots of information to the power system,” he said.
“So 1.3 is very much like the VR13 and VR14 specifications from Intel that does essentially the same thing but PMbus is more about system level issues than just the core voltage,” he said.
“An update to version 1.3 is in the works to accommodate multiple slaves