Cadence Design Systems has launched the industry’s first comprehensive static timing/signal integrity analysis and power integrity analysis tool, which enables engineers to create reliable designs at 7nm and below.
The Tempus Power Integrity tool is the result of an integration between the widely used Cadence Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution. Using the tool, chip designers can significantly lower IR drop design margins without sacrificing signoff quality, thus improving power and area. Early use cases demonstrated that the Tempus Power Integrity Solution correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10 percent.
“IR drop analysis is a key signoff technology that is increasingly critical, especially for today’s high-speed chips operating with highly resistive lower metal layers,” said Marlin Frederick, Jr., Fellow, Physical Design Group at Arm. “Our evaluation of the Tempus Power Integrity Solution highlights that Cadence’s integrated approach provides better coverage than traditional vector-based flows for reasonable amounts of compute.”
The Tempus Power Integrity tool supports smaller IR drop margins to improve power and area: Intelligent activity generation and direct calculation of the timing impact of IR drop reduces the need for larger safety margins, optimizing power and area. Vectorless activity generation automatically develops activity vectors for full coverage while also exploring potential failure scenarios on voltage-sensitive paths. THis helps to improve the signoff IR drop analysis reliability.
This proprietary vectorless-based algorithm also helps to identify voltage-sensitive paths. The machine learning (ML) techniques identify critical paths most likely impacted by IR drop to provide a high degree of IR drop analysis coverage without requiring extensive, time-consuming vectors.