Lattice moves to programmable FD-SOI for low power FPGA platform

December 11, 2019 //By Nick Flaherty
Lattice Semiconductor has launched an FPGA architecture aimed at the Internet of Things (IoT) where the FD-SOI silicon fabric can be tuned for power consumption.
Lattice Semiconductor has launched an FPGA architecture aimed at the Internet of Things (IoT) where the FD-SOI silicon fabric can be tuned for power consumption.

The Nexus platform is aimed at AI for IoT, video, hardware security, embedded vision, 5G infrastructure and industrial/automotive automation.

The Nexus platfrom is developed on high-volume 28 nm fully-depleted silicon-on-insulator (FD-SOI) process technology from Samsung. This cuts transistor leakage by 50 percent compared to bulk CMOS and a programmable back bias enabled by the insulated gate of the FD-SOI technology allows the performance to be optimised for the power requirements within the design tool.

“The Lattice Nexus platform augments the parallel processing and re-programmability of FPGAs with the power-efficient performance demanded by today’s technology trends, like AI inferencing at the Edge and sensor management. The platform also accelerates the rate at which Lattice will release future products,” said Steve Douglass, Corporate Vice President, R&D, Lattice Semiconductor. “Additionally, the Lattice Nexus platform offers easy-to-use solution stacks targeting high-growth applications that help customers more quickly develop their systems, even if they are not expert in FPGA design.”

The first device in the platform is the CrossLink-NX for communication interface designs.

The LIFCL-40 has 40,000 logic cells with 170bits of memory for each cell in a 1V array. Power consumption in an FPGA is notoriously hard to quantify, and Lattice points to the Power Calculator in the Lattice Design Software for estimating and calculating current as the operating and peak current is design dependent and some blocks can be placed into low current standby modes.

The device IO configures in 3 ms, and the rest of the device in under 15ms.

The family has two hardened 4-lane MIPI D-PHY transceivers at 10 Gbps per PHY, as well as up to 37 programmable source synchronous I/O pairs for camera and display interfacing. It is packaged in a 4 mm x 4 mm WLCS package (0.4 mm pitch) up to a 17 mm x 17 mm BGA package on an 0.8 mm pitch.

In addition to its new Lattice Radiant 2.0 design software, Lattice offers a library of


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