Interposer embeds capacitor to shrink package size

June 01, 2021 // By Nick Flaherty
Interposer embeds capacitor to shrink package size
Researchers at the Tokyo Institute of Technology develop a 3D functional interposer containing an embedded capacitor.

The compact design of the interposer, which links a silicon die to a substrate, saves a third of the package area and greatly reduces the wiring length between the chip's terminals and the capacitor. This reduces the signal noise and the power consumption, paving the way to new semiconductor package structures with greater miniaturization.

In modern 2.5D packages, chips such as DRAMs and microprocessors sit on the interposer with through-silicon vias, vertical conducting tunnels that bridge the connections in the chips with solder bumps on the package substrate. Capacitors are placed on the package substrate close to the components they serve, and a connection between their terminals and those of the chip has to be made, spanning 5-30 mm. This layout not only increases the necessary package substrate area, but also causes problems such as high wiring resistance and noise due to the long interconnections.

Instead, the team, led by Professor Takayuki Ohba, have made the interposer into a functional capacitor. The capacitive elements are embedded inside a 300 mm silicon piece using permanent adhesive and mold resin. The interconnects between the chip and the capacitor are made directly with through-silicon vias and without the need for solder bumps.

"Our bumpless 3D functional interposer enables a notable reduction in package area of about 50% and an interconnect length a hundred times shorter," said Ohba.

The researchers also managed to avoid the two most common problems of bumpless chip-on-wafer designs, namely warping in the wafer due to the resin and misplacement errors due to void pockets in the adhesive.

Through testing and theoretical calculations, they determined their functional interposer allowed for a wiring resistance about a hundred times lower than conventional designs, as well as a lower parasitic capacitance. These features could enable the use of lower supply voltages, leading to lower power consumption.

"The chip-on-wafer integration technology we are developing will open up new routes in the evolution of semiconductor package structures," said Ohba.

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