Samsung Electronics has launched an integrated power management IC (PMIC) for the fifth-generation double data rate (DDR5) dual in-line memory module (DIMM).
One major design improvement for DDR5 involves integrating the PMIC into the memory module, as the previous generations placed the PMIC on the motherboard. This provides increased compatibility and signal integrity, and providing a more reliable and sustained performance.
For improved performance efficiency and load-transient responses, the S2FPD01, S2FPD02 and S2FPC01 PMICs integrate a high-efficiency hybrid gate driver and a proprietary control design with a asynchronous-based dual-phase buck control scheme.
This scheme allows the DC voltage to step down from high to low with a fast transient response to changes in the output load current and adapts the conversion accordingly to efficiently regulate its output voltage at near-constant levels. The control scheme also features both pulse width and pulse frequency modulation methods, preventing delays and malfunctions when switching modes.
“With enhanced power efficiency and low output ripple voltage, the S2FPD01, S2FPD02 and S2FPC01 allow data centres, enterprise servers and PC applications to take full advantage of their DDR5 performance for highly demanding, memory-intensive tasks,” said Harry Cho, vice president of System LSI marketing at Samsung Electronics.
The S2FPD01 and the S2FPD02 are aimed at data centre and enterprise servers that run heavy analytics, machine and deep learning, and other various computing tasks in real time. The FPD01 is designed for modules with low density; FPD02 for higher density. The S2FPC01 is designed in a 90nm process for desktop or laptop PCs to fit into a smaller package.
By implementing a high-efficiency hybrid gate driver instead of a linear regulator, the PMICs operate at up to 91 percent power efficiency.
Samsung’s DDR5 DIMM power management ICs, the S2FPD01, S2FPD02 and S2FPC01, are currently being sampled to customers.
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