Industry's first SoC power-aware hardware emulation system

May 14, 2021 // By Nick Flaherty
Industry's first SoC power-aware hardware emulation system
The latest ZeBu EP1 system includes power aware emulation of software at speeds up to 10MHz.

Synopsys has launched a new version of its Zebu hardware emulation system, adding in power awareness for the first time.

The Zebu EP1 provides 10 MHz performance to speed hardware and software verification of complex system-on-chips (SoCs) in areas such as high-performance computing (HPC), 5G, GPU, artificial intelligence (AI) and automotive.

The emulator uses a direct connect architecture with Xilinx Virtex UltraScale+ VU19P FPGAs to achieve the speed for testing software on emulated hardware, giving power metrics for PCI Express (PCIe) 5.0, USB3, SATA, Ethernet, and NVMe-based designs with up to 2bn gates.

"We continue to accelerate innovation for our verification hardware by collaborating with industry-leading customers," said Manoj Gandhi, general manager of the Verification Group at Synopsys. "ZeBu EP1 represents the convergence of multiple hardware and software technologies to deliver breakthrough performance and debug. The unique fast emulation capability in ZeBu is enabling electronics companies to develop and verify the most advanced SoCs with full software stacks."

ZeBu Empower emulation system, the industry's first SoC power-aware emulation system, enabling multiple iterations per day with actionable power profiling in the context of the full design and its software workload.

Hybrid Emulation with Virtualizer virtual prototyping, supported by a library of virtual processor, memory and interface models, delivers 70-100x throughput gain for OS boot enabling more complex software validation and earlier tape-out.

Virtual Host and Device models for PCIe 5.0, USB3, SATA, Ethernet, and NVMe enable validation of host to device software stack with real OS, driver, and application software of complex SoCs.

Speed Adapters connect ZeBu emulation systems to real-world environments for in-circuit emulation (ICE) use cases. These are based on Synopsys DesignWare IP and support PCIe, CXL 2.0, Ethernet, USB, SATA, Display port as well as 5G testers, networking testers and customer specific hardware.

"Computing innovation is happening at a rapid pace across the Arm partner ecosystem," said Tran Nguyen, senior director of design services, Arm. "As more software-intensive Arm-based HPC, 5G, GPU, AI and automotive applications are developed, there is an increasing demand for faster emulation and accelerated verification, and we continue to work closely with Synopsys to address that need for our mutual customers."

"Xilinx and Synopsys' deep technical collaboration over many years has accelerated broad industry adoption of and innovation around FPGA-based emulation and prototyping," said Vamsi Boppana, senior vice president, Central Products Group at Xilinx. "With the growing complexity of SoC designs and software, we look forward to continuing our close work with Synopsys to advance a strong technology pipeline for FPGA compile, runtime performance and at-speed debug."

www.synopsys.com

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