The power interconnect on a chip is traditionally made through back-end-of-line (BEOL) processing on the frontside of the wafer. But researchers at imec in Belgium are moving the power distribution to the backside of the silicon wafer to allow direct power delivery to the standard cells, and promises to enhance system performance, increase chip area utilization, and reduce BEOL complexity.
Imec has shown at the VLSI Symposium this week that backside power delivery turned out to be the most efficient way of delivering power to the circuits. For example, it largely improves the supply-voltage (or IR) drop that is caused by a resistance increase in the BEOL of traditional designs. In a processor design using the approach with ARM, the backside power delivery is connected to a buried power rail (BPR), a structural scaling booster in the form of a local power rail that is buried in the chip’s front-end-of-line.
However this is a more complex way of delivering power. A dedicated wafer thinning process is needed in combination with the ability to process nano-through-silicon-vias (n-TSVs) that electrically connect the backside to the frontside of the device wafer.
The researchers looking at how this backside wafer processing could impact the active devices that are already present in the wafer’s frontside and how efficient voltage regulation and power conversion techniques can be implemented that are compatible with backside processing as well as the I/O.
Five papers presented at the 2021 VLSI Symposium show the progress in developing the critical technology building blocks needed for realizing backside power delivery networks as a structural scaling booster for Moore’s Law. Using the back of the wafer can create a very dynamic design space with new design options to optimize the power delivery for scaled systems.
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For the first time, imec has evaluated the impact of backside wafer thinning and n-TSV fabrication on the characteristics of scaled Si-channel FinFET test devices (gate length ≥20nm), built in the wafer’s frontside. The backside connectivity was realized through tungsten-filled n-TSVs that land on metal-1 pads in the wafer’s frontside. “The most important conclusion of this work is that wafer thinning and n-TSV processing in the backside did not show any negative impact on the performance of the FinFETs, except for a slight degradation of the pMOS drive current,” said Naoto Horiguchi, director CMOS device technology at imec. “For nMOS, an even higher mobility and drivability (up to 15 percent) were found after backside processing, and no bias temperature instability (BTI) degradation was observed. In this work, wafers were thinned down to final Si thicknesses ranging between 20 and 370nm.”
The wafer thinning and via-last n-TSV fabrication processes used in this study are being developed and optimized in the frame of imec’s 3D integration program.
“First, an epitaxial stack of Si/SiGe layers is grown on top of a bulk Si substrate. The SiGe layer later serves as an etch stop layer for ending the wafer thinning,” said Eric Beyne, senior fellow, VP R&D and program director 3D system integration program at imec.
“The frontside, including the FinFET devices, is then built on top of this Si ‘capping’ layer. Cu metal-1 metallization completes the frontside processing,” he said. “Next, the wafer is flipped over, and the ‘active’ frontside of the wafer is bonded to a second ‘carrier’ Si wafer using a low-temperature wafer-to-wafer bonding technique. The backside of the first wafer can now be thinned down to where the SiGe etch stop layer is located. Thinning down to a few 100nm is required to expose the high-aspect ratio nano-meter scale TSVs. After SiGe removal, the process is completed by n-TSV patterning and tungsten fill, and backside metallization.”
With this approach for backside power delivery, n-TSVs electrically connect the backside metal-1 to the frontside metal-1. Their electrical performance was successfully verified in specific n-TSV configurations (such as daisy chains). The n-TSVs can alternatively land on buried power rails implemented in the wafer’s frontside. Process steps for this challenging configuration are under development.