A fully integrated on-chip DC-DC converter design in 180nm CMOS by ETH and STMicroelectronics reaches 1.25GHz
efficiency from 70μW to 0.5W with less than 0.7 percent change, making the design suitable for various load conditions.
The researchers point out that 180nm CMOS does not provide a good balance of efficiency and high power density simultaneously due to the large parasitic capacitance of the switches and the low Q-factor of the transformers built with aluminium. Despite this, the technique enabled a high power density of 1W/mm 2 .
The technique also scales to more advanced technology nodes with a smaller gate capacitance, positively impacting both the efficiency and power density.
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Picture:
Two versions of the integrated on-chip DC-DC converter shown at ISSCC
