Free power management chips on multi-project wafers

July 07, 2020 //By Peter Clarke
Free power management chips on multi-project wafers
Designers can get digital power management ICs manufactured for free with support from Google, SkyWater Technology Foundry and eFabless.

The free offer from the FOSSi Foundation (Free and Open Source Silicon) is open to any power management and low power chip designers on condition that the design must be open-source and be published in detail down to the GDS tape level.

Tim Ansell, a software engineer at Google, used a Youtube video organized by FOSSi, known as a Dial-Up Talk, to announce that an open-source PDK for SkyWater's 130nm manufacturing process is now available. This includes a 30V high voltage (HV) 130nm library for power management chip designs and is characterised for capacitors and inductors. 

"An open, manufacturable PDK was the main blocker in a fully open flow between RTL and a physical chip, and we're extremely excited to see that blocker removed," said the FOSSi Foundation.

Google is also paying for US design management company eFabless to organize the sending of designs to SkyWater Technology Foundry and for a series of open-source multiproject wafer (MPW) shuttle runs there. Each shuttle run will have about 40 design slots and the first is scheduled for November 2020.

The MPW shuttle runs are completely free of charge, said Ansell. Users will receive of the order of between100 and 400 packaged ICs. Ansell added that the PDK is available to be cloned at GitHub with no non-disclosure agreement to sign. However, if users want to contribute to the PDK there is a something to sign with Google, he added. eFabless said it would make design with the PDK easy by integrating numerous resources on its cloud-based design platform.

Each design slot comes with a RISC-V core, power circuitry and RAM occupying about 6 square millimeters and a further 10 square millimeters available for open-source designs, including new power management designs, to be implemented.

Ansell said that right now the digital standard cells including the HV library are available but that the project intends to add analog and RF circuits, and compilers for


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