First radiation hardened single chip LDO for satellite power

January 30, 2020 //By Nick Flaherty
First radiation hardened single chip LDO for satellite power
The monolithic ISL70005SEH radiation hardened two channel synchronous buck converter and low drop out LDO regulator from Renesas reduces component count for satellite FPGA and DDR memory designs

Renesas Electronics has launched the first single-chip synchronous buck and low dropout (LDO) regulator targeting low-power FPGAs, DDR memory and other digital loads for spaceflight payload applications.

The ISL70005SEH is a point-of-load (POL) chip that integrates a synch buck and LDO in one monolithic chip to enable satellite manufacturers to reduce bill of materials (BOM) and power supply footprint for their medium Earth orbit (MEO) and geosynchronous Earth orbit (GEO) long duration mission profiles. Renesas uses the Intersil branding for its space and military products.

The ISL70005SEH synchrnous DC-DC buck converter has a 95 percent efficiency and is combined with a 75mV dropout on the LDO regulator. This enables easier thermal management for systems with 3.3V or 5V power buses and can support 3A continuous output load current for the buck regulator and ±1A for the LDO. The buck regulator uses a voltage mode control architecture and switches at a resistor adjustable frequency of 100kHz to 1MHz, enabling a smaller filter size.

“The ISL70005SEH gives satellite manufacturers the superior radiation performance, and SWaP and BOM savings they want,” said Philip Chesley, Vice President, Industrial and Communications Business Division at Renesas. “Our dual output POL regulator also provides the configurability to address multiple applications in commercial telecommunication satellites, military satcom satellites, and science and exploration missions.”

The space-grade ISL70005SEH simplifies design configuration allowing designers to use it as a dual output regulator, DDR memory power solution or high efficiency low noise regulator for RF applications. The flexible LDO can source and sink current and accept input voltages as low as 775mV to reduce unnecessary power dissipation. The externally adjustable loop compensation on the buck allows users to achieve an optimal balance of stability and output dynamic performance.

The device is wafer acceptance tested to 100krad(Si) over high dose rate (HDR) and tested for ELDRS up to 75krad(Si) over low dose rate (LDR). Single event radiation effects (SEE) testing shows no single event latch-up (SEL) and


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