EPC takes eGaN testing past AEC-Q101

February 26, 2019 //By Nick Flaherty
EPC takes eGaN testing past AEC-Q101
Efficient Power Conversion (EPC) has released its tenth reliability report on the performance of enhanced mode gallium nitride (eGaN) devices, taking it beyond current automotive standards with new test hardware.

Because GaN is a new semiconductor technology compared to traditional silicon MOSFETs, many customers request additional testing beyond standard automtoive AEC-Q101 standards, as well as a deeper understanding of the unique mechanisms that could lead to device failures. The Phase 10 report continues the accumulation of reliability statistics and research into the fundamental physics of failure in GaN devices.

The report shows automotive AEC-Q101 qualification on four new eGaN devices, with several more in the pipeline for release. AEC-Q101 demands the highest level of reliability standards for power FETs, requiring not only zero datasheet failures, but also low parametric drift during stress testing. The report presents in detail the test matrix that was completed to achieve this qualification.

The company has developed several new reliability tests for the devices, with one for the reliability of eGaN FETs under hard and soft switching conditions at high input voltages (VIN). Using a novel test system developed at EPC, the RDS(on) of parts operating in switching conditions can be measured and this can extrapolate any increases in RDS(on) (also called “dynamic RDS(on)” ) over 10 years of continuous operation. The switching reliability is measured against three acceleration factors: (1) VIN , (2) temperature and, (3) switching frequency.

Expanding upon the gate reliability studies discussed in Phase 6 report, EPC also developed new test hardware that allows populations of parts to be tested under DC gate stress, while allowing each part to be continuously monitored in time during the stress duration. Not only is gate leakage monitored continuously, but other device parameters (V TH and I DSS) can be logged on regular intervals. This data gives a more complete picture of device degradation under high gate stress conditions and provides visibility to multiple independent physical failure mechanisms.

The Phase 10 report also covers the failure statistics for a wide range of gate bias and temperature conditions and use the results to derive the dominant acceleration factor and activation

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