Design kit dramatically reduces PMIC power and die size

March 23, 2020 // By Nick Flaherty
Tower Semiconductor has launched a 180nm, 24V design kit with a 35 percent efficiency improvement with an RDSon of 6mΩmm²
Tower Semiconductor has launched a 180nm, 24V design kit with a 35 percent efficiency improvement and lower RDSon of 6mΩmm²

Tower Semiconductor has launched design kits for 180nm process technology for PMIC power management ICs that increases efficiency and reduces die size.

The kits provide scalable operation of up to 24V for consumer, industrial, automotive, and computing markets. This complements the Company’s previously announced low-voltage, 65nm Power BCD process, as well as its high-voltage 140V Resurf bulk and 200V SOI technologies.

The technology builds on six generations of 180nm power management platforms and the company says it is largely backward compatible making it easy to port existing parts and designs to the more efficient process.

“We are very excited to announce the release of design kits for this novel technology that provides our customers with breakthrough performance not available elsewhere,” said Shimon Greenberg, Vice President and General Manager of Power Management Business Unit, Tower Semiconductor. “We are committed to continue our investment in developing and providing best in class Power Management technology enabling our customers to bring to market advanced products and gain share in this large and growing segment of the semiconductor market”.

The lower Rdson of 6mΩmm² and a high breakdown voltage at all operating conditions provides enhanced reliability for PMIC designs for applications such as DC-DC converters, load switches, PMIC and motor drivers used in laptop processors and fans, drones and robotic motor drivers used in the consumer, computing, automotive and industrial markets.

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