Backside of the wafer promises 3D chip improvements

May 20, 2019 // By Peter Clarke
Backside of the wafer promises 3D chip improvements
European research institute IMEC has identified several innovations that could help establish 3D integration of circuits as the new normal at geometries below 10nm.

IMEC fellow Eric Beyne, 3D program director, and Julien Ryckaert, program director of 3D hybrid scaling, laid on the numerous options that are either already pursued commercially, or could be soon, in a meeting with press ahead of the IMEC Tecnology Forum.

With the increased difficulty of planar miniaturization integration in 3D has been pushing its way on to the agenda for a number of years. However, a lack of support for 3D design from EDA companies has somewhat hampered adoption. In addition, such developments as CoWoS [chip-on-wafer-on-substrate] and InFO [Integrated Fan-Out] packaging offered by TSMC while offering high-performance integration have only appealed to a few customers.

As a result the volume of manufacturing that would drive EDA companies and packaging companies to support the technology has been hard to achieve.

However, the exponentially increasing cost of planar integration is compelling the search for alternatives. This is one of the things that is driving the increasing adoption of 2.5D integration for logic and memory (see TSMC preps for 'chiplet' style manufacturing in 2021).

Beyne portrayed a spectrum of 3D integration opportunities that spans eight orders of magnitude for circuit interconnect pitch density from the millimeter scale to the nanometer scale.

The 3D interconnect technology landscape. Source: IMEC

The highest-level technique is the stacking of packaged components. Next is the use of multiple die in a single package using a passive interposer, this is known as 2.5D integration. Next is die-stacking using microbumps, which is at about the same level of interconnect density as wafer-to-wafer bonding prior to dicing. Beyond this we enter the realms of in-fab processes such as wafer-to-wafer sequential processing and transistor stacking.

Some transistor stacking has been attempted in the commercial world with 3D NAND memory with up to 96 layers being the most obvious, but a specialized, example (see Samsung ramps production of 96-layer 3D-NAND flash).

Next; Beyne and Ryckaert go further

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