Backside power key to Intel process

July 27, 2021 // By Nick Flaherty
Backside power key to Intel process
Providing power connections from the back of a wafer is a key technology for Intel going forward

Intel's process technology plans have highlighted the role of backside power technology. 

This provdes power from the back of the wafer, avoiding the need to route large power lines over the top of a chip and enabling a smaller die. This has been pioneered by imec in Belgium.

Backside power articles on eeNews Power 

The key change is the A-series process nodes from 2023. The 20A process will be the equivalent of 2nm, starting in the middle of 2024, and will use two breakthrough technologies, RibbonFET and PowerVia.

PowerVia is Intel’s version of the backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer and so reducing the die size and cost of devices. Intel 20A is expected to ramp in 2024 and the company is working with rival Qualcomm on how to use this process technology a part of Intel’s foundry offering.

RibbonFET is Intel’s implementation of a gate-all-around transistor that Samsung is already using for its 3nm production. This will be the company’s first new transistor architecture since it pioneered FinFET in 2011. This provides faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint.

Before then, the recent technology announcement renames the current 10nm process to Intel7, and the Intel4 process in 2022 with products in 2023 will compete with TSMC’s current 5nm process which will see an optical shrink to 4NP in the same timeframe. Intel3 will be ready to begin manufacturing products in the second half of 2023 using extreme ultraviolet (EUV) technology.

Beyond Intel 20A, Intel 18A 1.8nm equivalent is already in development for early 2025 with refinements

The backside power stack proposed by Intel

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