Anatomy of a secure power management design

February 21, 2020 //By Nick Flaherty
Researchers at Rice University in the US have developed a new technique for power management that makes chips in the Internet of Things more secure.
Researchers at Rice University in the US have developed a new technique for power management that makes chips in the Internet of Things more secure.

The security of devices in the Internet of Things is an increasingly important area of development. While microcontrollers used in the IoT have added AES encryption units, these are still vulnerable to side channel attacks (SCA) via the power consumption and electromagnetic emissions to crack encryption keys. So a team at Rice University's Brown School of Engineering led by Kaiyuan Yang, an assistant professor of electrical and computer engineering, have used the power management regulators in the chip to obscure the EMI.

Low-Dropout Regulators (LDOs) are commonly used to give fine-grained power management in IoT chips with a small die area, high current efficiency, and small output ripple. Digital LDOs (DLDOs) are increasingly adopted in recent years thanks to voltage and process scalability. However, achieving a fast response to a load change requires a conventional synchronous DLDO to either increase its sampling frequency with a large power overhead, or include a large output capacitor (COUT) with increased chip area and cost.

Voltage regulators are also found to be useful in enhancing the resistance of cryptographic engines and processors against such SCA attacks. Using regulators for SCA defence in power management is promising because they are already used in most systems and require no modifications to existing computing architectures and algorithms like other circuit-level defences.

The team at Rice designed a 65nm SCA-aware DLDO using a new technique called an  Edge-Chasing Quantizer (ECQ) that essentially ‘smears’ the EMI randomly to make it less detectable.

The DLDO prototype developed by Yan He and Kaiyuan Yang achieves a 101.7mV droop and 506ns settling time after a 20mA, 0.1ns step load change, with only a 0.1nF capacitor and occupies 0.018mm2 active area and 99.4 percent peak current efficiency.

The DLDO consists of an ECQ, a second path booster, a digital controller, a PMOS switch array and a 10b output register to eliminate switching glitches.

The ECQ quantizes the input-voltage difference using an even-stage ring


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