Agile Analog ships configurable power IP

December 04, 2019 //By Peter Clarke
Agile Analog rolls out power IP products
Analog IP startup Agile Analog (Cambridge, England) is rolling out power IP designs for various CMOS and FDSOI manufacturing processes.

The voltage and current sensors and low drop out (LDO) regulator power IP is highly configurable for 180nm CMOS processes down to 22nm FDSOI. FDSOI comes in 28nm versions from STMicroelectronics and Samsung and at 22nm from Globalfoundries.

Agile Analog claims that its approach to analog design has advantages over the conventional manual, superset design of analog circuits in use today. The method is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable, Agile Analog claims. Other advantages include that process updates can be applied at a later stage, and IP can be designed and verified with the most up-to-date physical design kits.

Licensees select the power IP circuit type and then configure against specification. The customer also selects for manufacturing process. The IP is then generated and delivered along with documentation, integration and test guides.

Other IP includes ADCs, DACs, temperature sensors, oscillator clocks, threshold comparator and charge-pump and body-bias generator.

The company was founded in 2017 and is led by two former ARM executives.

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