Researchers in the US and Japan have developed a synthesis tool for adiabatic logic that has 10,000 times the energy efficiency of current FinFET devices and nearly 50,000 times better performance than 40nm CMOS.
The research team used a digital logic process called Adiabatic Quantum-Flux-Parametron (AQFP). This technique uses alternating current rather than direct current with a clock and power rails. The alternating current acts as both the clock signal and the power supply, so that as the current switches directions, it signals the next time phase for processing.
The adiabatic logic can be used to reduce the power in transceivers with current silicon fabrication process technology, reducing the power consumption in data centres and supercomputers particularly.
"The significant amount of energy consumption has become a critical problem in modern society," said Olivia Chen, assistant professor in the Institute of Advanced Sciences at Yokohama National University. "There is an urgent requirement for extremely energy-efficient computing technologies."
The team developed an automatic synthesis framework to translate from high-level logic description to AQFP circuit netlist structures. This was used on 18 circuits, including 11 ISCAS-85 circuit benchmarks, 6 deep-learning accelerator components and a 32-bit RISC-V ALU. The synthesis results demonstrate the significant advantage of AQFP technology with a boost of 9,313×, 25,242× and 48,466× energy per operation compared to TSMC's 12 nm FinFET and 28 nm and 40 nm CMOS process technologies. The ALU in 40nm consumed 1410 fJ, compared to 0.04 fJ for the AQFP adiabatic logic.
"This showed that AQFP can achieve a reduction in energy use by several orders of magnitude compared to traditional technologies," she said.