Engineers designing high-performance computers and servers being used in large data centres are increasingly using 48V rack-level power distribution systems to provide more energy efficincy. The reference design, which follows the principles of the Open Compute Project (OCP). supports a flexible and efficient point-of-load power implementation backed by a multi-vendor ecosystem.
The board for Intel’s upcoming first volume 10nm processor will enable design engineers to evaluate the power stamp concept and specific point-of-load stamps from dc-dc vendors. It can help to accelerate the project development cycle for new server designs and other equipment using the latest Intel processors in a 48V rack environment. The PSA has also developed a board suitable for the Intel VR13 (Skylake) processor architecture and a board for ASIC devices. The Power Stamp Alliance has a roadmap for future reference design boards for processor architectures used in high-performance computing.
The board is being shown at the OCP Summit 2019, supported by founding Members, Artesyn Embedded Technologies, Bel Power Solutions, Flex, and STMicroelectronics.