28nm FD-SOI i.MX8 targets low power

March 03, 2021 // By Nick Flaherty
28nm FD-SOI i.MX8ULP targets low power
The i.MX8ULP from NXP adds a flex domain for power management and is the first to be built on a low power 28nm FDSOI process

NXP has launched an ultra low power version of its i.MX8 processor with security enhancements.

The i.MX 8ULP family is the first to be built on a low leakage 28nm FD-SOI process technology to reduce the static power, and adds a flexible power management architecture to lower the dynamic power.

The Energy Flex architecture delivers as much as 75% improved energy efficiency than its predecessor by allowing access to individual blocks. Rather than using traditional dynamic voltage scaling on separate power domains, Energy Flex uses a RISC-V core to control access to blocks in the ‘flex domain’.

These GPU and DSP can be switched on and off separately from the processor and microcontroller cores. This allows an A/D converter to provide data to a GPU without having to wake up a power-hungry processor, or power down from sleep mode to deep sleep without having to power up the operating system to do so.

The RISC-V subsystem can govern more than 20 different power mode configurations from full power down to 30 microwatts, and additional custom configurations can be defined, says Mohit Arora, director of architecture for low power MPUs at NXP.

The family will use single or dual core ARM Cortex-A35 application gigahertz processor cores that can run Linux or Android alongside a 266MHz ARM Cortex-M33 for real time operating systems. Other blocks include a Cadence Tensilica HiFi4 DSP for machine learning and advanced audio processing, and/or a Fusion DSP for low-power voice and sensor hub processing as well as a Verisilicon graphics processor unit (GPU) for 2D and 3D graphics.

NXP has also added its EdgeLock secure enclave to the chip with self-managed, autonomous on-die security. This is a pre-configured security subsystem that simplifies implementation of complex security technologies such as silicon root of trust, run-time attestation, trust provisioning, SoC secure boot enforcement and fine-grained key management augmented by extensive crypto services for advanced attack resistance, while also simplifying the path to security certifications.

The EdgeLock secure enclave intelligently tracks power transitions when end-user applications are running on the device to help prevent new attack surfaces from emerging.

The secure enclave will be a standard feature across the i.MX 8ULP and another version, the i.MX 8ULP-CS, that is designed to be part of the Microsoft Azure Sphere cloud service for security management.

The i.MX 8ULP-CS adds Microsoft Pluton’s software on the EdgeLock secure enclave as the secured root of trust built into the silicon itself, and as a key step toward enabling highly secured devices for a vast range of IoT and industrial applications. In addition to the secure hardware, the chip can run the secured Azure Sphere OS with ten years of security updates.

Next: related NXP i.MX articles


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