Enpirion: An engineer’s guide to the key steps to powering an FPGA design

By Enpirion
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The latest FPGAs and SoCs can require up to 90 A of current and multiple power rails that need careful consideration on power up. Read More


FPGAs are fast becoming the key component of many embedded designs due to their dynamically reconfigurable fabric and parallel processing capability. These features make these semiconductors ideal for use in systems in application areas such as convolutional neural networks and machine learning, broadcast communications equipment, and advanced driver assistance systems (ADAS).  Likely to interface with a plethora of other components and sub-systems in addition to supporting devices such as transceivers, PLLs and memory, the FPGA typically needs multiple supply voltages, each with their own unique requirements in terms of voltage, current and transient response. For example, the FPGA core is likely to require in the 10s of Amps, with some designs now requiring up to 90 A at relatively low voltages, e.g. 0.95 VDC, while memory, interfaces and legacy logic will have requirements in the range 1.5 to 3.3 VDC. Considerations such as noise immunity are also important in the design of the power supply. Transceivers, and PLLs in particular, need to have extremely clear power rails in order to prevent jitter entering the system.

 

Figure 1 – An example early power estimator (EPE) for an FPGA-based design (Source Enpirion)

Faced with powering a new FPGA or SoC design, the engineer is advised to compile a list of all the required voltage rails together with other key critical parameters such as peak current. Another key aspect of any complex design is the need to group or sequence the power on and power down of the individual power rails. This ‘tree’ list illustrated in Figure 1 above shows an example of all the power requirements. Attention should be paid not only to the various output voltages, but also to the incoming supply. Presenting all these criteria together allows the power engineer to start architecting the power supply design.

In today’s space constrained applications, a designer must assess the physical space available and determine whether there is enough to accommodate the full mechanical design. For example, an engineer may need to add fans for forced air cooling, an element that has a major impact on the conversion efficiency of the overall power supply. The power engineer also must evaluate the area available for a high power supply and determine if it is physically possible to incorporate a discrete power design, or whether to opt for a compact space-optimised power regulator module. Discrete designs have long been seen as a potentially lower cost option, but power modules are increasingly seen as a much better cost, space, and performance alternative. However, accommodating the space required by a discrete circuit needed for a 0.95 VDC / 60 A supply as illustrated in Figure 1, may simply not be possible.

The engineer should also reference the FPGA device’s datasheet or application note for the specific pin connection guidelines stipulated for the core and transceiver rails. This information provides details regarding line regulation tolerance, its temperature specs, and the transient response required by the device’s individual power rails. It is recommended that attention be paid to determining the choice of regulators required for the FPGA core and the transceivers. Depending on the main supply voltage, an intermediate bus converter may or may not be required.

In the case of Intel PSG’s Arria 10 GX device, the power pin connections guide also gives a recommendation to how the power to the device is supplied giving options for the number of regulators used. The core supply voltage for this device is 0.9 VDC will a +/- 30 mV supply tolerance. Figure 2 highlights the power supply scheme for an Arria 10 GX device using two regulators. Note that the power tree scheme needs to also accommodate the power up / power down grouping required.

 

 

Figure 2 – Example power supply scheme using two regulators (Source Enpirion)

In the above example, the supply tolerance equates to 1.5% or better, so the power engineer needs to research suitable power modules to achieve that. To provide maximum flexibility and control of the power conversion change, selecting regulator modules that can be digitally controlled are recommended, which aids the power up/power down and facilitates full monitoring.

Figure 3 – Example regulator module –Enpirion EN63 (source Enpirion)

An example of a regulator module is the EN63xx series from Enpirion. This series includes a high efficiency DC-DC step-down converter with an integrated inductor and delivers an outstanding combination of power density and conversion efficiency.  For example the EN6362QI is a 6A converter that integrates power switches, inductor, gate drive, controller, and compensation in a small 8 x 8 mm QFN package. The conversion efficiency enables the EN6362QI to deliver 6A continuous operating current across the full industrial operating temperature range.

Once the core and the transceiver regulators have been chosen, the rest of the power tree regulators can be chosen based on all the key parameters. A summary of all the power requirements should be pulled together as illustrated in Figure 3. The efficiency of each regulator needs to be calculated in order to determine whether power from any intermediate bus converter is required.

 

Figure 4 – Example of power tree scheme

At this stage in the power scheme design, attention can be given to the sequencing requirements. As mentioned above, the FPGA application guide will highlight any specific power-up and power-down sequences that need to be adhered to. The example highlighted in Figure 5 shows the need for three different power groups to be sequenced and the voltage points at which the next groups can commence power-up.

 

Figure 5 – Power-up and power-down sequence

The power-down process is the reverse of power-up process. It requires the design engineer to note the time that is required to discharge capacitors within the power tree. To accomplish this discharge power, MOSFETs should be employed to accommodate the largest capacitance bank in the power scheme. Clearly, it is crucial that the MOSFETs used for charge are capable of handling the transient power experienced during the discharge process and that they will operate within safe parameters that do not cause excess thermal stress. One way to manage the power-up/ power-down sequence could be to use a FPGA device such as Intel PSG’s MAX10 device. Figure 6 illustrates a simple schematic diagram of the circuitry required to achieve this with a group of four power rails. An auxiliary power supply would be needed to power the MAX10 shutdown circuit sequence process for at least 100 ms after the start of the power-down process has been activated.

Figure 6: a simple schematic diagram of the circuitry required to achieve power up with a group of four power rails

By using the steps covered above a power engineer will be ready to design a power scheme for a complex FPGA design.


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