Tower expands 65nm power process to 24V
Tower Semiconductor has launched the second generation of its 65nm BCD power LDMOS process technology, expanding the voltage to 24V and reducing the on resistance by 20%.
It is also adding deep trench isolation (DTI) to its 180nm BCD platform, enabling a 40% smaller die for designs running up to 125V.
Reducing the RDS(on) by 20% from the current 1mΩ*mm² for 12V BVDSS allows designs in the 65nm process to trade off power performance and/or die size reduction by up to 20%. This is aimed at monolithic high-power converters, including high-power voltage regulators for CPU and GPUs in addition to applications such as chargers high-power motor drivers and power converters.
The 180nm BCD deep trench isolation scheme (DTI) improves noise immunity within a single chip. The flexibility to select between multiple isolation schemes up to 125V helps reduce the die size by up to 40% for 48V systems that require ICs to hold voltages up to 120V.
Market researchers Yole Développement predict the power management market will reach over $25.5bn by 2026. Tower is in the process of being acquired by Intel.
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