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TI claims fastest 16-bit DAC at 1.5 GSPS

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By eeNews Europe

The DAC34SH84 offers increased bandwidth with the device’s 750-MSPS-per-DAC input rate supporting up to 600-MHz complex bandwidth for fifth order linearization of 120 MHz – three times wider than the competition when running at maximum sample rates.   

The frequency agility of the device sees 2x to 16x interpolation.  Two independent, 32-bit numerically controlled oscillators lower the interface rate and cost of FPGAs while providing flexibility in frequency planning.

The DAC34SH84 also offers RF sideband image suppression benefits.  On-chip calibration of complete RF transmit path suppresses sideband and local oscillator feed-through while driving IQ modulators, such as the new TRF3705.

The DAC34SH84EVM evaluation module can be purchased for $499. The device includes transformer-coupled IF outputs to evaluate the DAC34SH84 directly.

For complete bits-to-RF transmitter prototyping, the TSW30SH84EVM includes the DAC34SH84 in addition to the TRF3705 IQ modulator; LMK04800 ultra-low jitter clock cleaner; TI power management devices, such as DC/DC converters and low-noise LDOs; and a power amplifier.

For sourcing patterns at high speeds into the DAC34SH84EVM, the new TSW1400EVM pattern generation module, also announced today, features a high-speed, double-data rate LVDS (low-voltage differential signaling) output bus that provides 16 bits of data at 1.5 GSPS per bit. When combined with the DAC34SH84EVM or TSW30SH84EVM, the TSW1400EVM enables modulated pattern generation with a large on-board memory while offering a flexible evaluation environment.

An IBIS model to verify board signal integrity requirements is also available.

The DAC34SH84 is sampling now in a small 12-mm x 12-mm BGA package. Production quantities are expected in 2Q 2012.

The TSW1406EVM pattern generation module provides a lower-cost alternative for simple pattern generation up to 1 GSPS per bit. The module will be available in March 2012.

www.ti.com/dac34sh84-preu


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