Team takes ‘Finfet’ GaN transistors to 1200V and beyond

Technology News |
By Nick Flaherty

The researchers from IQE, MIT, IBM and Columbia University in the US and the Singapore-MIT Alliance for Research and Technology have developed a new design that allows GaN devices to handle voltages up to 1200 volts. The team believes that further work can boost its capacity to the 3300 to 5000V range for operation in the electricity grid directly.

“All the devices that are commercially available are what are called lateral devices,” says Tomás Palacios, MIT professor of electrical engineering and computer science and a member of the Microsystems Technology Laboratories. “So the entire device is fabricated on the top surface of the gallium nitride wafer, which is good for low-power applications like the laptop charger. But for medium- and high-power applications, vertical devices are much better. These are devices where the current, instead of flowing through the surface of the semiconductor, flows through the wafer, across the semiconductor. Vertical devices are much better in terms of how much voltage they can manage and how much current they control.”

This provides more space for input and output wires, enabling higher current loads, higher voltages and higher efficiencies.

“When you have lateral devices, all the current flows through a very narrow slab of material close to the surface,” he said. “We are talking about a slab of material that could be just 50nm in thickness. So all the current goes through there, and all the heat is being generated in that very narrow region, so it gets really, really, really hot. In a vertical device, the current flows through the entire wafer, so the heat dissipation is much more uniform.”

Vertical devices have been difficult to fabricate in gallium nitride. Palacios and the team use bladelike protrusions, or fins, to create a FinFET transistor. The narrowness of the fin ensures that the gate electrode will be able to switch the transistor on and off.

“The brilliant idea, I think, was to say, ‘Instead of confining the current by having multiple materials in the same wafer, let’s confine it geometrically by removing the material from those regions where we don’t want the current to flow,'” said Palacios. “Instead of doing the complicated zigzag path for the current in conventional vertical transistors, let’s change the geometry of the transistor completely.”

The work was presented at the IEDM conference this week.

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