Sub 1-V low noise high PSRR LDO with improved load transient
By combining implemented logarithmic current feedback and transient peak limiting circuits with the introduction of the parallel high speed amplification at fast varying load condition in main error amplifier (EA) great load transient and power supply rejection ratio (PSRR) can be achieved with excellent stability upon the entire load current range.
The design has been performed in 0.18 µm technology using special techniques in order to guarantee sub-1V operation of this LDO. The LDO is suitable for use in low power application with fast varying loads such as power supplies in portable electronic devices.
LDOs have become one of the most widespread power converters in portable electronics. As the integrated circuits (ICs), especially digital ones, keep increasing the number of transistors per square according to Moore’s law and thus reducing the size of single components, new challenges arise for both LDOs and supply circuits as a whole.
Modern digital circuits require the power supply to be effective (eg low power consumption), have good load transient due to fast varying digital signals, and be able to work at low voltage levels providing stable outputs well under 1 V as with the decreasing component sizes their working voltage domains decrease as well.
As for analog and mixed signal circuits such as ADCs, lighting and sensor circuits, apart from the requirements mentioned above PSRR and noise performance become critical parameters for the supplies.
Several techniques exist for improving load transient performance of LDOs. This includes AB class output stage error amplifier (EA) for driving pass device’s gate capacitance [Ref 1], adding a source follower as a buffer between amplifier and pass transistor [Ref 2], inclusion of an additional current amplifier in a feedback loop to accelerate reaction of LDO [Ref 3].
There is also a variety of possibilities to make LDO capable to work in a sub 1V domain ranging from integration of a digital controlled loop as in [Ref 4] to deliberate decrease of transistors’ threshold voltages (VTH) by using body effect phenomenon [Ref 5]. However it is not simple to combine any of the cases to get both improved load transient and low voltage operation in a single LDO. In current paper an effort is taken to fulfil such a combination in a working solution. Moreover in order for the LDO to be able to supply analog as well as digital loads special architecture and additional circuitry were added in the realisation in order to improve PSRR and noise performance.
As a result a universal low input low output regulator with the improved load transient was achieved that was capable of supplying not only digital but also mixed and purely analog circuits.
Concept of the proposed LDO
The current section will present the choice of the proposed LDO’s architecture with special focus on the main parameters: load transient, low voltage operation, PSRR and noise.
In order to improve the load transient a well known structure was selected as a basic concept shown in Fig. 1, where two amplifiers connected in parallel are used for a driving pass device.
Fig.1. LDO structure with two error amplifiers connected in parallel
In this structure the main amplifier A1 can be a standard two stage amplifier. It determines the main parameters of the LDO. Since A1 is not used for fast driving of power transistor (MP), it can have an A class output stage.
The feedback resistors Rf1 and Rf2 determine the output voltage of the LDO. The second amplifier should have a wide bandwidth and preferably an AB class output stage for fast charging of the power transistor’s parasitic capacitance.
The output of the amplifier A2 is connected to the output of the amplifier A1 and to the gate of the power transistor MP. The LDO output is connected to the non-inverting input of A2 and to the lowpass filter (LPF). The output of the LPF is in its turn connected to the inverting input of the amplifier A2. This connection creates zero voltage between inputs of A2 in steady state condition and excludes the influence of the amplifier A2 on the DC parameters of LDO.
During fast variation of the LDO’s output load the inverting input of the A2 does not change its value if LPF’s time constant is larger than transient time of load variation. The non-inverting input of A2, however, follows the LDO’s output voltage and starts compensating its variation. Amplifier A1 reacts significantly later because of its low bandwidth. After a certain time which exceeds few time constants of LPF, the A2 is again in steady state condition and does not influence the operation of the LDO [Ref 6].
From the load transient performance standpoint the presented structure is acceptable. However it is not well suited for low voltage operation as it is not simple to design a high bandwidth sub-1V operational amplifier (op-amp) with an AB output stage due to biasing. This requires implementation of complicated techniques including the minimum selector circuit, increase in number of stages followed by a complex stabilisation. All this gives a dramatic rise in quiescent current (Iq) which is not particularly good for portable applications [Ref 7].
Another limitation of this concept is its noise performance. Fig. 2 represents the most significant noise sources of the relevant structure.
Fig.2. LDO’s major noise sources
From the work done in [Ref 8] the total output noise spectral density of the LDO system Sn,o(f) is represented by
It can be seen that the most significant noise sources in this LDO are the reference produced noise at vref node, EA noise and noise associated with output resistor divider (Rf1, Rf2). The A2 amplifier is not operating during normal condition (if no load transient occurs) thus the amount of noise generated by it is negligible and is not included here.
In order to adjust the selected methodology to low voltage operation and reduce the number of sources generating noise to the output without degradation of other performance, significant changes were needed to be made to the original concept. The new updated structure can be found in Fig. 3.
Fig.3. Updated LDO structure
First of all, voltage selection which is performed by a resistive divider was moved to the reference path. The reference amplifier was included as well as varying the upper resistor. This way the needed output voltage can be easily selected by changing the resistance ratio. LPF in the reference path is used to suppress noise to the EA input stage, while the amplifier itself operates as a voltage follower with unity gain [Ref 9]. In this way the reference induced noise and noise associated with the resistor divider are mostly filtered out and total output noise from (Equation 1) becomes dominated only by the EA’s noise.
Another change was made in the LDO’s feedback. Apart from voltage feedback common for all conventional LDOs, a direct current feedback was implemented by integration of a current sensing element (MS) parallel to the power pass transistor. This action provides better stability and PSRR for moderate values of current. Finally the parallel amplification function, which was explained earlier, was integrated inside the EA through a peak detection (PD) function.
Design and implementation
The circuit was designed using the 0.18 µm 1.8 V CMOS process with typical threshold voltages of PMOS and NMOS being VTHP =-500 mV and VTHN = 470 mV. Input voltage VIN can range from 0.9 V to 1.8 V while output can be regulated down to 0.65 V. All the blocks inside the LDO except MP and MS can be supplied either from VIN or from a separate supply, making it ideal to be used as a post-regulation LDO. In order to get a better view of the blocks’ design it is more practical to examine them separately.
Reference amplifier and filter
For total output noise suppression the structure described in detail in [Ref 9] was used. The main idea of this approach is to isolate reference and resistive divider noise sources with a lowpass filter Fig. 3.
The main limiting criterion of reference amplifier design is input voltage which should be as low as possible. An A class operational amplifier with NMOS FET input pair is used in proposed architecture and depicted in Fig. 4.
Fig.4. NMOS input two-stage operational amplifier
In this structure minimum the input voltage can be defined as
In case of an A class operational amplifier with a PMOS FET the input pair minimum input voltage is the same as in (Equation 3). However the maximum common mode voltage of NMOS amplifier is
and for PMOS amplifier
Thus VCMMAX in NMOS amplifier is approximately one VTH larger than in case of PMOS input pair. LDO output voltage of the proposed architecture can be calculated by
For normal operation of reference amplifier its reference voltage should be Vref < VCMMAX. Thus the choice between NMOS and PMOS input pair is dictated by available reference voltage value.
The proposed LDO architecture with an error amplifier structure operating as a voltage follower put forward an additional requirement for the reference amplifier output stage type. In conventional LDO architectures low dropout operation is mainly determined by output power FET resistance and load capability. Since in the proposed structure output voltage is created in reference block (see Fig. 3), only the PMOS transistor can be used as the output FET of the reference amplifier. In addition its resistance should be small enough to pass current determined by resistive divider without significant voltage drop.
As this structure is concentrated on low output noise and the main noise sources have been described above, the reference amplifier together with resistive divider are isolated with low pass filter with ultra high time constant (approximately 1 second).
To achieve such time constant the filter output resistance should be in the range of GOhms, but this would occupy a significant silicon area when using passive resistor. In current approach the low pass filter is implemented by a very high resistive MOS transistor as resistor with a capacitor of order of tens to hundreds picofarads Fig. 5. The filter capacitor can be either poly/poly cap or a MOS transistor (more area effective).
Fig.5. Reference low pass filter’s schematic
The MOS resistor is relatively simple and is a very area effective approach for large value resistors. The main problems are related to the high ohmic output of the filter. This means that any leakage above 1 pA cause inadmissible errors. Since the PMOS resistor is placed in a n-well, which is connected to the input of the filter (a low resistive node), the leakage between the resistor and n-well is suppressed (Fig. 5, Fig. 6). The MOS resistor pn-junction, connected to that high ohmic node, should not leak because of zero bias. No other pn-junctions are connected to that node except a startup transistor, which is a similar MOS resistor with much lower resistance, biased exactly the same way (zero bias on pn-junction connected to high ohmic node).
Fig.6. Reference low pass filter’s MOS resistor
For the particular technology oxide leakage is far below 1 pA. But any other possible disturbances to that high ohmic node can cause failure of the reference. These can be current leakage or other disturbance caused by light emission, EMI, etc. However, this approach is area and noise effective and depends on final compromise of the filter resistance and capacitance values.
Error amplifier and current feedback As the EA in a newly formed structure works as a voltage follower, i.e. regulated voltage at the output of LDO is fed back directly to the EA’s input; the common mode voltage (VCM) should be able to swing up to the supply or at least very close to it, so that low dropout operation could remain functional. For that reason simple two-stage Miller compensated amplifier with NMOS input pair, like the one used as a reference amplifier, served as a basis for EA design (Fig.4). The maximum common mode voltage in this amplifier is (4). This way VCMMAX is still slightly lower than VDD.
In order to increase VCMMAX, the original structure was modified. Additionally current feedback circuit was introduced in order to ensure good PSRR and stability on the entire load current range. The updated structure can be seen on Fig.7.
Fig.7. Updated error amplifier structure
In this newly formed amplifier transistor M9 eliminates the need for M4 to have voltage drop higher than VTH, while M7 serves as level shifter for gate of M6, thus keeping the amplifier in normal working region. The cascoded M2 and M3 were included for PSRR reason, the working principle of which will be explained later. This decreased VCMMAX by VDSsat however 2VDSsat of M2 and M4 is still smaller than VTH across M4 in Fig.4. As a result the maximum common mode voltage changed to
This means that input of the OP-AMP can be safely swept up to supply without degrading the amplifier’s performance.
Another reason for the changes in the original circuit is VDDmin optimisation. The inclusion of the cascoded M2 and M3 added a VDSsat to VDDmin and became a limiting factor for a sub-1V operation, but the elimination of the diode-connected PMOS in the load path of the input stage has cancelled this limitation.
PSRR here is increased in two ways: introducing M2, M3 in cascode with main input pair and current feedback. To understand how cascodes help increase PSRR it is better to examine the main LDO’s structure in Fig.3 as well as the amplifier’s circuit. The reference for the main input of the EA is taken after the noise filter so that reference and resistive divider induced noise is filtered out. If the cascodes had not been included in the first stage of EA, a significant drain-gate capacitance of M0 would deliver high frequency (HF) disturbance caused by the supply into the filtered reference path causing PSRR’s degradation. Cascoded M2 however uses its drain-gate capacitance to form HF path from supply to the filter’s input. In this case all the unwanted HF chattering is filtered out by noise LPF.
The way current feedback operates is rather simple. VGS of MP and MS (Fig.3) are equal. Not taking into account channel length modulation, the current densities of these transistors are also equal. Although this is a very rough approximation and the accuracy will suffer, it still should be enough for this particular application. With this approach the load to sense current ratio can be written as
If MP and MS are scaled by coefficient K, currents through these transistors will be scaled in the same way [Ref 10].
IS is fed into EA where current feedback circuit uses it to adjust bias currents I2 and I4 proportionally to the load current. This manifests in increase of amplifier’s gain and bandwidth with increasing load which improves PSRR in this condition.
Apart from improving PSRR current feedback has another very important purpose of ensuring stable operation throughout the entire load range. For a 2-stage OP-AMP to be stable there is a direct need that a non-dominant pole (fnd) should be kept at the possibly high frequencies, at least three times higher than unity gain frequency (fG0). This is achieved by implementation of Miller capacitance CC. If bias currents I2 and I4 are scaled proportionally, then the needed relation fnd=3 fG0 will be kept valid. With this type of frequency compensation a right half plain (RHP) zero (fz) may be present which is better to avoid. The common way to abolish the RHP zero is to introduce a resistor RZ like in Fig.4 with following condition
where gm6 is the transconductance of the amplifier’s second stage, which in this case is transistor M6. If (11) is fulfilled fz moves to either infinity if RZ=1/gm6, or to the left half plain (LHP) if RZ>1/gm6. In the later case for the bandwidth performance not to suffer the fz should not be significantly higher than fG0. fz=3fG0 is a good relation in that sense. The final choice of RZ could be in the range
The choice of RZ value would have been relatively simple if gm6 and gm0 were constant however they vary with load due to bias current tuning. This means that RZ value should also be adjusted so that condition (Ref 12) would stay valid. For that reason RZ is connected in parallel with M8 (Fig.7) which in its turn is controlled by the current feedback circuit so that with the increase of load current M8 resistance decreases in logarithmical order. This way with no load, M8 is closed and the compensation resistance is fully determined by RZ and at different load conditions M8 RDSon is adjusted in such a way that (Ref 12) is accurately fulfilled.
Due to low bandwidth of the main error amplifier LDO is not able to react properly on fast load variation. For LDO load transient improvement a peak detection circuitry is used (shown in Fig. 8).
Fig.8. Error amplifier with inclusion of peak detection circuitry
Due to low input voltage the peak detector structure described in [Ref 6] and shown in Fig. 1 is not the best option. It is not able to operate at low input voltages as since it is limited by VTH. The proposed peak detector architecture is based on a common source amplifier and is able to operate at high range of input voltage. This amplifier has wide bandwidth and operates at high frequencies only, where load transient event takes place, while low frequencies are rejected by the capacitor at its input. PD_IN input is the output of the LDO. During load transient event the LDO output voltage changes its value and wide bandwidth peak detector charges/discharges gate capacitance of the power FET by transistors M10 and M12. Charging/discharging current depends on the output voltage variation. The more output voltage varies, the larger current is generated for driving power FET.
The proposed LDO solution was realised and fabricated in silicon. Consequently its functionality and all the parameters were verified not only by simulations but also by measurements. Layout view of the LDO can be found in Fig. 9.
Fig.9. Layout of the proposed LDO
Fig.10. Load transient response of the proposed LDO
Fig.11. PSRR performance of the proposed LDO
Additionally to that the use of low noise architecture resulted in 17 μVRMS total noise integrated over the range of 10 Hz to 100 kHz. All the LDO’s main parameters are summarised in Table 1.
The presented work had the aim to combine so far non-combinable features like low voltage operation, high PSRR, low noise and good load transient response in a single LDO. In order to achieve this goal a separate action was taken to improve each of the above mentioned parameters. First, special low noise architecture was implemented to improve noise performance. The introduction of current feedback and peak detection circuits helped to achieve the needed PSRR and transient response while ensuring stable operation on the entire load current range. Finally special care taken in the error amplifier design process completed the low voltage operation of the LDO. As a result a sub 1 V low noise high PSRR LDO with improved load transient was designed and fabricated that is ideally suitable for post regulator application capable of supplying both analogue and digital loads.
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