Reliability report highlights GaN board performance

Technology News |
By Nick Flaherty

The Phase Eight Reliability Report showing the results of the rigorous set of JEDEC-based qualification stress tests eGaN FETs and integrated circuits undertake prior to qualification

Product-specific detailed stress test results for over millions of actual device hours are provided. In addition to product qualification stress testing, due diligence is necessary in other areas of reliability such as field experience, failures over device operational lifetime, and board level reliability. The three sections of tests covered in the eport include Field Reliability an dassembly failtures, Early Life Failure and Wear-out Capability, and Board Level Reliability and Thermo-mechanical Capability

“Demonstration of the reliability of new technology is a major undertaking and one that EPC takes very seriously,” said Dr. Alex Lidow, CEO and co-founder of EPC and the co-founder of International Rectifier, noow part of Infineon. “The tests described in this report, along with the reported results, show that EPC gallium nitride products have the requisite reliability to displace silicon as the technology of choice for semiconductors.”

he previous report, Phase Seven, documented 17 billion device operation hours with a very low failure rate below 1 FIT (failures per billion hours) for stress-based qualification testing. The broader tests of Phase Eight examined returns form the field from 8 m device-hours of testing. 

EPC pioneered the adoption of chip-scale packages for GaN high power and high voltage applications, and this can present a learning curve for reliable board level assembly. The chip-scale fine pitch solder geometry (400 µm – 1000 µm), relatively low standoff height (~ 100 µm), and exposed die require proper assembly techniques, and this resulted in device assembly and handling accounting for the highest number of field returns at 75 units.

Improper control of the amount of solder paste and flux released during assembly, together with inadequate rinsing and curing of the flux, made up 36 of the field failure units, while die corner chipping was found to be the cause of failure for 27 units in the field. This is a consequence of eliminating the molded plastic surrounding the die, leaving it exposed to the environment. 

For a total of 12 field failures of the actual devices, the root cause was related to a circuit design issue. Eleven of the field failures were damaged due to the electrical overstress resulting from voltage overshoot in a circuit layout that had too much parasitic inductance. Transient overvoltage can lead to device degradation observed as increased leakage currents or on state resistance, as opposed to DC overstress conditions which typically show up as completely inoperable devices.

The full report is here 


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