Semefab in the UK has produced samples of a new quantum tunnelling transistor and wafer process that could cut lead times, wafer area and process layers while increasing speed, reducing power and increasing gate density over CMOS.
The transistor architecture developed by startup Search For The Next (SFN) in Nottingham, UK, uses quantum tunnelling (above) rather than insulated gates. This architecture, called Bizen after the combination of bipolar and zener, allows logic to be produced in just eight layers on a standard CMOS process, rather than 20 to 30 for standard CMOS transistor designs. Test chips on a 1μm process produced by Semefab in Glenrothes, Scotland have cut the lead time from 15 weeks to three, and the die area is a third the size of a comparable CMOS device on the same process, said Allan James, CEO of Semefab, in an interview with eeNews Power
Quantum tunnelling is not new, as it is widely used in NOR flash memory chips. But with Bizen the technique has been applied to logic devices, proven by Semefab and extended to work with power devices.
“The integration of conventional lateral and vertical bipolar structures can, with careful modelling, be designed to incorporate Bizen without undue additional process complexity,” James told eeNews Power. “I was initially quite sceptical but having lived with the concept and seen early-stage results, it does indeed tick many of the boxes needed to disrupt the industry. It’s not so much a question that CMOS is flawed – although CMOS is prone to latch up and ESD. CMOS is low power, has passed the test of time and is generally reliable. However, it is complex and when integrated with power even more so. Complexity means longer lead times and higher cost.”
Next: Quantum tunnelling transistor channels
The three independent quantum tunnelling channels in the device allow the interconnect between the transistors to be in the active layers, rather than using the metal layers. This reduces both the footprint and the layer count, which in turn reduces the lead time. The transistor is Normally-On but not saturated, and is controlled by an isolated tunnel connection, rather than a direct metal contact to the base well, as used in traditional bipolar transistors.
Beacuse it uses quantum tunnelling, the architecture relies on a current swing, typically around 300 to 400mA, rather than a voltage swing, for the logic. This leads to lower power consumption and also alternative computational architectures such as analogue computing.
“Because we don’t have a base connection, we connect to the well of the transistor like a FET, although a FET has an isolated gate and we connect to the gate using a tunnel instead,” said David Summerland, CEO of SFN. “It is heavily doped so we don’t have high voltage, and symmetrical so we can push the current through.”
This is the key starting point for the basic transistor, he says. “This means we can do an XOR in 2 transistors, and a flip flop in 8. We can change the tunnelling by area, bias voltage or doping – and we have two orders of magnitude on doping left for scaling,” he added.
There is also a significant advantage in noise immunity. This allows the logic gates to be implemented alongside NPN and PNP power transistors, or even within the structure of the power device.
Next: Quantum tunnelling spice models
The Spice models for a range of devices have been completely rewritten by the team at SFN, which includes researchers from the University of Nottingham. There is also a complete physical design kit (PDK) for the Cadence design flow, says Summerland.
The current approach allows for analogue computing, where currents can be combined and grow over time, and this is one of the first products for early in 2020. “The Programmable Junction Transistor (PFT) means we can integrate high voltage and logic on the same die in 8 layers without using a SOI substrate,” he said. “It has been difficult to get the combination of power and logic, and if it is just logic its less layers.”
“We will release the PJT in Q1 and Q2 and that’s where we expect to get fab uptake on the process,” he said. “We believe the process will scale beyond 1um but that’s not proven yet. We are actively looking at a scaling project and our simulation says it will.”
This could open up logic production at older fabs that are already producing power devices. “If it can be adopted by the industry, an important prize given the reduction in die area at a given technology node comparing a Bizen and CMOS logic implementation would be the ability to wind back the Moores’ Law clock by 10 years or more and bring many wafer fabs back into mainstream manufacture,” said James. “There is still a way to go before Bizen becomes a commercial reality and we are still learning, however Semefab and SFN are working flat out to make it the huge success it may soon become.”