Power chiplet boosts high performance system-in-package designs

Power chiplet boosts high performance system-in-package designs
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Wavious has launched the WPM100, a power chiplet that supplies up to 15A with clock PLL and Gen5 PCIe
By Nick Flaherty

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US chiplet specialist Wavious has launched a power management chiplet for next generation AI systems.

The WPM100 provides power management and clocking in a chiplet die measuring 2.0mm x 1.8mm.​ This is designed to meet the precise voltage and fast transient requirements of high-performance circuits and includes high switching-frequency DC-DC regulators, LDOs, PLLs to generate a wide range of clock frequencies, up to 5GHz, available on 3 differential output drivers.

Using a chiplet for power management allows a power process to be used and each WPM100 can provide up to 15A total current and up to 12 power domains. This works with WTM monitors to provide an optimal supply level and improve the power optimisation alongside chiplets for other functions such as high performance processing and machine learning alongside memory devices. These can be assembled on an interposer for a system in package design in six months rather than and SOC that might take two years.

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The WPM also includes PCIe Generation3, 4 and 5 reference clock generation as well as data converters. The WPM also supprts rapid custom chip prototyping or expansion of systems by selecting die from the range of Wavious chiplets

Established in 2015, Wavious now has over 25 engineers between San Diego and Raleigh. COO Jason Thurston has previously managed analogue design teams at ARM, Qualcomm and RapidBridge Technology, while CEO Benny Malek was VP of engineering at Qualcomm and CTO at RapidBridge

www.wavious.com

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