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Pareto analysis of GaN cost savings in the data centre

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By Nick Flaherty



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While existing silicon designs have improved steadily in efficiency and density, there’s a limit to what can be achieved with this technology. This is where gallium nitride (GaN) devices are being increasingly employed to meet the challenging requirements of the data centre market with respect to density and efficiency.

Over recent years, there’s been a shift towards computing being handled in the cloud, which has led to an unprecedented growth of hyper scale datacentres with ever more power to be handled per rack. In turn, this has meant power demands have increased with the focus being laid upon more efficient, compact power supplies that use less electricity. Heat dissipation is the other essentially element here, with the aim to minimize the cooling demands as far as possible. With power demands for each rack rocketing up to 20kW and higher, there has been a trend away from the conventional 12V power rails to using 48V, thus reducing losses. However, more improvements are needed.

GaN devices have a number of electrical characteristics that give them advantages over silicon. Firstly, GaN high-electron-mobility transistors (HEMTs) have an order of magnitude lower gate charge and output charge, as well as virtually zero reverse recovery charge. Together, this means that hard commutation of reverse conducting devices is possible, thus enabling the use of simpler topologies such as totem pole PFC stages with trapezoidal current modulation.

By reducing switching losses and allowing higher switching frequencies, GaN devices can deliver higher efficiency than silicon alternatives in many applications, as well as higher power densities. On the downside, GaN switching devices are more expensive than silicon alternatives, and may increase the overall power supply cost.


Investigating costs and efficiency

One of the industry’s natural concerns is whether this potentially higher initial capital expenditure (CapEx) for GaN-based power supplies can be justified. To examine this, it is necessary to review the total cost of ownership (TCO) of similarly designed solutions based upon both GaN and Si devices.

This is obviously quite challenging to prove, bearing in mind the quantity of different parameters that could influence the performance of a power supply. One method to approach this analysis is using a Pareto optimization, a method that systematically considers multiple objectives in an engineering design. In this case, the key results of focus would be efficiency, power density, and TCO.

This approach provides a systematic way to evaluate multiple parameters, such as combinations of components in differing topologies or configurations, and to choose the optimal solution. This avoids the need to rely on ‘gut feel’ or rough calculations and allows us to simultaneously investigate the trade-offs between different factors more accurately.

For instance, a GaN-based solution might achieve an efficiency of 98.1 percent, compared to 97.6 percent for a silicon alternative. The increase in efficiency might sound small, but it means losses are cut by a fifth (from 2.4 percent to 1.9 percent). Despite this, it may be difficult to evaluate if that improvement is worthwhile without using Pareto optimization.

A typical telecoms power supply was considered that has a nominal input voltage of 230VRMS and provides an output voltage of 43V to 58V (with a nominal value of 54V), as shown in Figure 1. One example also defines a maximum output power of 3kW and a hold-up time of 10ms at this power. It should be noted that, even though we chose a telecom power supply for this example, the results can also be applied to datacom power supplies that provide 48V output voltage. As server power supplies typically include an additional ORing function, some small additional losses will, however, need to be taken into consideration.

Figure 1: Example power supply design

For this investigation, a power supply design with totem-pole power factor correction (PFC) and an inductor-inductor-capacitor (LLC) topology was used. For the GaN- based design, continuous conduction mode (CCM) with fixed switching frequency for PFC modulation was selected, while for the silicon-based system triangular current mode (TCM) for achieving soft switching was used. To simulate typical usage conditions, the behaviour at 50 percent load, 230Vin, and 54Vout was considered.

Assuming a usage lifetime of seven years with electricity costs of $0.10US/kWh and a power usage effectiveness (PUE) of the data centre of 1.5 takes into account a 25 percent gross margin for the power supply vendor. The calculations also factor in control losses, the cooling system, an estimated 20 percent volume of air as well as the space taken by components, and the costs of the casing, connectors, PCB and manufacturing.

Multi-objective Pareto analysis

To undertake the analysis, various options were examined at both component and system level. These included:

  • Numbers of totem-pole HF legs, EMI stages, parallel converter stages, and matrix transformers in LLC
  • Switching frequency of AC-DC stage (50kHz to 150kHz) and resonant frequency of DC-DC stage (50kHz to 350kHz)
  • Values of passive components
  • Inductor, transformer and capacitor design

By working through all of the possible design variants based on these variables it was possible to calculate the overall performance of every alternative. The simulation executed provided the efficiency, volume, and cost for each design, which can then be combined with the defined financial assumptions to calculate a value for TCO.

To deliver credible results, the simulations need to consider many different factors. These range from the electrical models, investigating how losses, volume and cost vary for different inductors, to thermal performance and the magnetic behavior of various components.

The analysis produces a ‘Pareto surface’, also called a ‘Pareto frontier’, that shows the optimal design choices that can be plotted graphically. For each of these optimum solutions, if any design factors were to be changed to improve one aspect of performance, another aspect will get worse. As in real life, there are trade-offs at each point that a design engineer can consider when choosing the best solution.

Analysis results

Evaluating the design for 54Vout from 230Vin, operating at 50 percent load, the efficiency and power density dimensions were initially reviewed (Figure 2). For each simulation of the GaN and Si-based designs a red (GaN) or blue (Si) point is placed on the graph indicating the efficiency and power density it achieved.

Figure 2: Efficiency vs power density for a range of GaN and Si 54Vout designs

From here the ‘Pareto-optimal’ solutions in terms of efficiency and power density for the Si and GaN designs were determined (Figure 3). This means that for any given value of power density, the design with maximum efficiency achieved is plotted.

Figure 3: Pareto-optimal highest-efficient GaN and Si designs compared

Here it is clear that the GaN solution has higher efficiencies at all power densities. In the high efficiency region, the advantage is around 0.4 percent, and in the high-density region (where efficiencies are lower) the improvement with GaN compared to silicon is around 0.8 percent. As well as this, the GaN-based design can achieve a maximum power density that is almost 10W/in3 higher than the silicon alternative.

From here the financial implications can be considered. To keep the graph to just two variables, designs were considered with a specific power density, in this case 80W/in3. It should be noted that similar results can be shown for other power densities too. By keeping power density constant, a graph can be plotted based on TCO (Figure 4).

Here TCO is normalized by considering the silicon design with the lowest initial costs (but not necessarily the lowest TCO), which forms the 100 percent line. The results plot how the TCO drops for both GaN and Si as the efficiency improves. It can be seen that the GaN-based solution delivering an efficiency of 97.35 percent also delivers a 13 percent TCO improvement over the best silicon design.

Figure 4: The most efficient 80W/in3 density GaN-based design can deliver a 13 percent TCO improvement versus the most efficient silicon design 

In addition to the significantly higher efficiency, less power is dissipated as heat, thus leading to lower electricity costs and reduced cooling requirements. This outweighs the higher initial costs of the GaN devices over an Si-based design.

Conclusion

Considering a power supply’s topology, components, associated costs and energy consumption, the Pareto analyses conducted by Infineon show that GaN-based switching devices can help achieve a lower TCO than silicon-based designs, at least in high density applications. As the market is shifting towards higher densities, this means the GaN advantage will grow further.

While the initial cost of a GaN-based power supply will be greater than that for a solution using silicon devices, the GaN solution will deliver benefits in terms of higher efficiency and more compact size, as well as reduced control complexity. By considering power supply investment in terms of TCO, rather than just CapEx, it can be seen that GaN-based solutions are where the focus should be for engineers sourcing power supplies in the coming years.

The exact financial benefits achieved will of course depend on the application and the specific electricity costs, but in today’s high-power telecoms and server applications, the GaN switching devices can deliver big savings. Almost as importantly, by using Pareto optimization, these savings can be demonstrated in advance, enabling a robust business case to be put together for a GaN-based solution that demonstrated how its cost will be amortized.

www.infineon.com


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