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Packaging advances match semiconductor progress in power converter miniaturisation

Technology News |
By eeNews Europe

Today’s electronic systems, especially those in areas such as telecommunications infrastructure, networking and data management, pack ever-more functionality into smaller and smaller profiles. The microprocessors and other highly-integrated ICs on which they are based require correspondingly greater levels of power, often at voltages that are lower, and currents that are higher, than ever before.

Power provision has evolved along with every other component and subsystem: regulation, distribution and voltage conversion have had to migrate on to the main system circuit boards and can no longer be designed as a separate entity. Advanced packaging designs shrink power-conversion functions enabling greater power integration with main board functions; dramatically improved efficiencies cuts losses to levels that make heat removal from those smaller packages, a practical endeavour.

Many of the trends in today’s systems were evident as long ago as the early 1980s – a convenient point in the context of this article, as it marks the period during which linear power supply topologies were being replaced by switching methodologies for the great majority of designs – and also saw the appearance of the “brick”, of which, more later. State-of-the-art design rules for chip fabrication were around 1.5 microns; parts already fabricated that you bought off the shelf, would likely be larger still. The change of semiconductor geometries that Moore’s Law has charted, from 1.5 microns to today’s leading-edge 22 nm, represents an increase in functional density of over 4600:1.

Figure 1: In three decades, commercial semiconductor processes for fabricating digital circuits have moved from the 1.5 μm node to the 22 nm node, shown here on a logarithmic scale (left).

Reduced silicon geometries drove integration, packing more and more functional blocks on to each chip. Beyond that, the chip integration story is largely one of packaging. The economically-optimal die size has not changed much – other than in the case of the largest and fastest processors, FPGAs and systems-on-chip. But compare an earlier-generation 40-pin DIP with today’s chip-scale-package, micro-BGA offering and the trend is clear to see.

Conversion efficiency enables high power density
Power supplies for electronic products have followed a parallel path, although not always in a smooth progression of diminishing size. The story is also one of increasing density over time and with it, efficiency. Ever-higher figures for Watts delivered from a given volume have gone hand-in-hand with efficiency; the losses (heat) dissipated by the typical supply of three decades ago could not be extracted by any practical technology from the volumes occupied by today’s power conversion blocks.

One small reference point can be judged by comparing a single device from “then” with a complete function “now”. A workhorse bipolar junction transistor of the 1970s, still widely used in the early ‘80s, was the 2N3055 or in its plastic-packaged form, MJE3055T. In its TO-220 form it would occupy a footprint of 16 x 10 mm (just one switch), not allowing for its through-hole terminations, and it was a 60 V, 10 A maximum-rated device. Today, we can draw 1.2 kW continuously from a single package on a footprint of 64 x 23 mm – and that is for the complete function, not just a single transistor.

While improvements in semiconductor switching performance (higher frequencies, lower device on-resistance), magnetics and architectures drove the early part of this trend, more recent improvements have also depended on advances in thermo-mechanical design, particularly of power management components.

Some formats from decades past remain in use, largely unchanged, today; for example, the “silver box” supplies that power desktop computers. A 400 W ATX12V features a largely discrete design (Figure 2). Individual heat sinks cool power MOSFETs and output rectifiers but the overall thermal design results in large thermal gradients, which are problematic at high ambient temperatures. With a typical efficiency of 80%, the 138 x 86 x 140 mm form factor provides a power density of only 0.24 W/cm3. High-quality ATX supplies designed to meet the “80-plus Platinum” specification endorsed by the US Energy Star programme can almost double that number to 0.42 W/cm3 but as a design approach, they fall far short of the density needed for telecommunications racks or server farm/data centre applications.

Figure 2: Traditional open- and closed-box power subsystems, including the ATX12V silver box power supply shown here, provide low power density and limited scaling potential.

Also, to serve today’s semiconductors, and the cards and racks that house them, power supplies must handle dramatically-increased load current dynamics, at low voltages and high currents. The physics of distribution over even short lengths of copper dictate that the final stage of regulation must be immediately adjacent to the load.

The era of the Brick
A number of alternative architectures arose in attempts to optimise power subsystems for various physical arrangements of loads. By no means coincidentally, the same era mentioned above (the early ‘80s) saw the first appearance of the “brick” or power conversion module. High up-time applications, such as communication line cards, replaced large, inefficient, multi-output supplies with distributed power architectures. These designs start (offline) with redundant single-output AC-DC converters to ensure that the reliability of the distributed voltage, typically 48 V, meets the system’s uptime requirements. Line cards usually use onboard brick converters followed by a number of small non-isolated point of load (POL) regulators to power individual resources.

Design of such systems can be challenging, and debugging or fault-finding problems with unexpected load-dependent behaviour, equally so. Largely discrete, forced-air-cooled power subsystems present uneven surfaces to the cool air source, resulting in turbulent airflow, which can lead to thermal shadowing and hotspots. Encapsulated brick converters, by contrast, use potting compounds to form essentially isothermal devices. Within the encapsulant, power devices thermally couple to an aluminium baseplate, which provides a single cooling surface. Cooling can be by conduction, forced-air convection, or a combination of both, with even and predictable effect.

Such a baseplate surface provides a large contact area for heat-sink attachment. This thermo-mechanical design allows 600 W maximum output power from a 117 x 55.9 x 26 mm package and 12.7 mm heat sink (inclusive) for a power density of 3.5 W/cm3 – an order of magnitude improvement over closed-frame silver-box designs. This was, however, only the first stage in a continuing story of progress.

As product functional densities continued to increase, the brick form factor quickly gave rise to fractionally-sized versions – half-, quarter-, eighth-, even one-sixteenth-brick – while successive generations provided increasing power handling capabilities. The fractional-brick’s shrinking cooling surfaces constituted a thermal challenge for system designs pushing both functional and power densities (Figure 3). This challenge was exacerbated in applications for which typical ambient temperatures were on the rise as was the case, for example, in server farms and communication hubs.

Figure 3: Fractional brick power management components offer decreasing baseplate surface areas while successive generations increase power density. Thermal challenges result when designs reach practical limitations of single-sided cooling methods.

Power provision comes on-board
The first such systems did, however, embody a philosophical shift in thinking that thereafter became accepted wisdom; namely, that the power supply could no longer be considered as a separate element but had to be designed as an integral sub-system of the main product. An evolutionary process followed in which a succession of power distribution architectures was developed to best exploit the peak performance available from the semiconductor devices and converter architectures of the moment. The number of power distribution buses, and the voltages they operated at; the locus of regulation; and where isolation should be implemented – all became variables, in shaping a power system to minimise losses, and to place the unavoidable losses where they could best be managed. Today, the designer has unprecedented freedom in making these choices and is able to choose from a menu of flexible power conversion functional blocks.

With electrical loads – heat sources – and power management components (dissipating heat in inverse proportion to their efficiency) co-located on system boards, thermal challenges grow with increasing operating temperature: Excess heat reduces the reliability of electronic components. Designers must derate power components for operation at elevated temperatures so, without effective methods of eliminating heat, power trains become over designed, resulting in larger, heavier, and more expensive systems.  Significant an advance as brick packaging technologies were, and while the brick form factors still play a role in terms of simplicity, the industry has grown to need even more dense power management devices beyond what can be accomplished with purely single-sided cooling.

Power moves to semiconductor-style packaging
One example of advanced packaging that improves power processing and delivery performance is the Converter housed in Package (ChiP) technology from Vicor. ChiP-based devices exploit symmetrical configurations placing dissipative devices on both sides of a central PCB. A thermally conductive encapsulant transfers heat to both the top and bottom surfaces effectively doubling the cooling surface area relative to the device’s PCB footprint (Figure 4). With appropriate system PCB design, additional heat can conduct through the electrical contacts as well.

Figure 4: Advanced packaging technologies, such as Vicor’s ChiP, support symmetrical thermal designs exploiting top- and bottom-side cooling.

These devices also reflect semiconductor technology in that they are built in an automatic process, in a large array on a single substrate, over-moulded together and then sawn into single-function blocks in an analogous way to a silicon wafer. Thermal symmetry is maintained by mirroring device layouts on each side of the substrate, and magnetics sit in cut-outs so that they have a facet on each surface of the finished device.

A combination of high efficiency – 98% peak for 380 to 12 V bus converters – and the symmetrical thermal design with advanced materials can provide power handling of 1.5 kW. One of the first such devices released to the market is the BCM bus converter. This is an unregulated DC-DC converter providing a fixed-ratio (8:1), isolated conversion. It was designed with DC distribution at 380 V in mind – another system attribute that would have been unlikely for the power designers working with the first bricks – to feed power into a conventional 48 V bus. It therefore accepts 260 to 410 Vdc on the primary bus, to deliver an isolated 32.5 to 51.3 Vdc unregulated secondary voltage.

With peak efficiency of up to 98% the device is an almost ideal “DC transformer”; in addition to low noise, fast transient response, it achieves 115 W/cm3 power density at 48 V. A package that measures just 63.34 mm x 22.80 mm x 7.26 mm can deliver a continuous 1.2 kW – that is 25 A at 48 V. A moment’s rule-of-thumb arithmetic shows that with losses held to just over 2%, there will be around 50 W of heat to dissipate: while not trivial, this is well within the capabilities of heat-management technologies that have evolved to handle high-dissipation microprocessors and SoCs – to which, of course, the package bears a marked resemblance.

And, while this is in large part a story of packaging innovation, circuit topology has not stood still. In addition to its other outstanding electrical specifications, this converter provides an AC impedance that exceeds the bandwidth of most downstream regulators, allowing input capacitance normally located at the input of a point-of-load regulator to be located at the input of the BCM module. Because a voltage-squared relationship is involved, that capacitance value can be reduced by a factor of 64x, resulting in savings of board area, material and total system cost. Also, the block is bidirectional; in terms of the normally-accepted architecture (distribution from 380 V to 48 V) power can also be returned to the 380 V bus.

Flexible cooling options

The packaging and over-mould is sufficiently thermally uniform that the device will operate to its full specification with single-sided cooling. However, its mechanical construction invites double-sided, clamped retention with heat drawn from top and bottom surfaces (Figures 5a, 5b) in which case even higher ratings can be achieved.

Figures 5a, 5b: Power management devices taking advantage of advanced packaging can deliver as much as 1.5 kW from cells measuring less than 10 in3 including heatsinks and fan.

As well as promoting efficient heat transfer the encapsulant provides a level of safety insulation commensurate with high-voltage power management requirements and international safety standards. This allows the same packaging technology to apply to a wide range of power management functions. These include AC-DC conversion with power-factor correction; isolated bus conversion; DC-DC conversion; buck, boost, and buck-boost regulation; and POL current multiplication. A single packaging technology that is applicable to the full menu of power management tasks from power entry to POL can also simplify system thermo-mechanical design by unifying device profiles and thermal characteristics.

ChiP BCM

Capabilities and scaling vary among various power component manufacturers, so check your vendors’ offerings carefully. In the case of Vicor’s ChiP-based components, devices can attain thin profiles to 4.7 mm and footprint areas from 6 x 23 mm to 61 x 23 mm, and expanding. Current capabilities extend to 180 A and operating voltages to 430 V, and rising. The company has demonstrated power delivery capabilities in this package technology as great as 1.5 kW, and that parameter will also increase.  

In lower-power applications such as POL converters, small-footprint, low-profile packages provide system designers with additional flexibility to minimise trace lengths from power converter to load. When powering digital resources characterised by high dynamic currents, such as ASICs, processors, or memory subsystems, low loss and low inductance power feeds ensure tight regulation and rapid transient response measured at the load, where it counts.

This type of packaging technology also supports high voltage-ratio converters, which in some applications can allow designers to eliminate an entire conversion stage, reducing system cost, increasing the power-train’s end-to-end operating efficiency, and increasing reliability.


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