Infineon Technologies has developed a new package technology for its Source-Down (SD) power MOSFETs operating from 25V to 100V.
The 3.3 x 3.3 mm PQFN package sets a new standard in power MOSFET performance, offering higher efficiency, higher power density, superior thermal management and low bill-of-material (BOM) for motor drives, SMPS for server and telecom and OR-ing, as well as battery management systems.
The latest Source-Down package technology enables a larger silicon die in the same package outline, reducing the RDS(on) on resistance and the package losses. This enables a reduction in RDS(on) by up to 30 percent compared to the previous Drain-Down package.
This smaller form factor allows designers to move from a SuperSO8 5 x 6 mm footprint to a PQFN 3.3 x 3.3 mm package with a space reduction of about 65 percent, enhancing the power density and system efficiency in the end system.
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Additionally, in the Source-Down concept, the heat is dissipated directly into the PCB through a thermal pad instead of over the bond wire or the copper clip. This improves the thermal resistance by more than 20 percent, from 1.8 K/W down to 1.4 K/W for simpler thermal management.
Infineon offers two different footprint versions and layout options: the SD Standard-Gate and the SD Center-Gate. The Standard-Gate layout simplifies the drop-in replacement of Drain-Down packages, while the Centre-Gate layout enables optimized and easier parallelization. These two options can bring optimal device arrangement in the PCB, optimized PCB parasitics, and ease of use.
The OptiMOS Source-Down power MOSFETs are now available in PQFN 3.3 x 3.3 mm 2 packaging, a wide range of voltage classes from 25 up to 100 V, and two different footprint versions.
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