New text book on RTL design by Atrenta

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By eeNews Europe

The book targets RTL designers and provides rich information on design practices and how they affect downstream implementation tasks. Topics discussed in the text include: reliable RTL construction, clock domain crossings and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling and routing congestion.

“The decisions made by RTL designers can have a profound impact on the schedule and ultimate quality of the chip,” said Sapan Garg. “Through the use of many examples, we highlight how the RTL designer can heavily influence the outcome of any design project.”

The book is available now through or at

Visit Atrenta at



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