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LLC synchronous rectification made easy, robust and more efficient

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By eeNews Europe

The green energy movement has brought about huge increases in efficiency to commercial AC/DC and DC/DC power supplies. The 80 Plus requirements stipulate that titanium-class power supplies must have a 97% efficiency from input to output. The results are that power supplies run cooler and more reliably, and save significant utility costs. Requirements like these are becoming commonplace. Anyone who has ever attempted to design one of these power supplies knows that synchronous rectification is a must.
 
This article explores a new synchronous rectification control method that leverages the intelligence present in modern digital controllers. This method has a synchronous rectification technique that seeks to minimize the dead time while constantly on the lookout for dead times that might present a hazard to the system. Since this method is inherently intelligent, it makes the design engineer’s job easier. Designers no longer have to perform a worst-case analysis to precisely predict all of the possible dead time conditions and, subsequently, include margin in their dead time settings for those conditions. The end result is faster time-to-market, better robustness and, most importantly, higher efficiency.
 
Introduction                                              

Nowadays, a resonant converter that uses two inductors (LL) and a capacitor (C), better known as LLC resonant converters are becoming popular for its ability to achieve high efficiency. This topology has been widely used in applications such as enterprise servers and telecom DC/DC converters. For high-efficiency operation, the secondary side rectification diodes are replaced with synchronous MOSFETs to reduce the conduction loss. However, controlling synchronous rectifiers (SR) is non-trivial – both the most optimized turn-on and turn-off edges should be right at the SR current zero crossing point, which moves depending on input voltage and load current. Turning-on/off too early or too late results in efficiency loss, negative current, or high drain-to-source stress. A lot of research and commercial products are focused on providing a good SR control method for LLC converters [1]. Figure 1 shows a half-bridge LLC resonant converter with SR MOSFETs.
 

 


Figure 1: Half-bridge LLC resonant converter with SR MOSFETs
 

State-of-the-art LLC resonant converter SR driving strategies fall in two categories: 1) MOSFET turn-on resistance (Rdson) voltage drop sensing-based method; and 2) SR pulse width clamp method, which usually is used in digitally-controlled LLC converters.
 
In the first method, the MOSFET is turned on after a large negative voltage on MOSFET body diode is detected on the MOSFET drain terminal. The MOSFET is turned off when the voltage drop on the MOSFET Rdson goes above a small negative voltage. Some commercial products in this category try to vary the gate drive voltage to enable fast turning off. Turn-on and turn-off blanking times are required in this method. This method doesn’t require a gate driver input and works for both analog and digital solutions. One of the drawbacks of this method is that the voltage drop on Rdson is often too small to detect due to low resistance, and varies with layout parasitic and the type of MOSFETs being used. Also, in high current applications where there are several MOSFETs in parallel, the Rdson is so small that the MOSFETs are turned off when the current is still large.
 
In the second method, the SR gate drive signal comes from the digital controller. The turn-on edge is usually fixed. The turn-off edge changes based on operation modes. At above or equal to resonant frequency, the turn-off edge varies, based on the switching frequency and keeps a fixed dead time relative to the primary side gate drive signal. At below resonant frequency, the SR pulse width is clamped to half of the resonant period minus some dead time. This method is easy to implement with digital power controllers. The drawback is that it requires resonant tank information for programming the pulse width clamp value and, thus, requires calibration. The calibration process often takes a long time in the production line, which makes production costs higher.

Table 1 is a summary of the two categories of state-of-the-art LLC SR control methods.

 

Table 1: State-of-the-art LLC SR control methods

 
A digital adaptive driving scheme for LLC SRs is discussed in reference 1. However, in this work, the SR turn-on edge is fixed and not optimized. It cannot handle the turn-on edge phase-shift at high switching frequencies. To better handle transient response, a clamp is implemented on the SR pulse width. The maximum SR turn-on time is delta T longer than the primary side pulse width, where delta T is a pre-programmed value.

However, this results in a transient problem: the SR turn-on edge is still the same with primary-side gate drive signals, but the turned-off edge is after the primary side. In this way, the SR pulse width will be longer than the primary side gate drive pulse width. This may result in a shoot through or drain-to-source overstress condition. Another issue is that there is no special detection region when transient happens. The SR on-time may adjust toward the wrong direction due to errors in body diode conduction sensing. We will talk about that a little more in a bit.
 
To overcome the previously mentioned drawbacks of the existing solutions, a novel body diode conduction time (DCT) sensing-based adaptive SR control method is proposed. The drain-to-source voltage on the MOSFET Rdson can vary with package, layout parasitic, and load current. But when the body diode conducts the voltage drop on the body diode it is relatively constant, regardless of parasitic and load conditions. The DCT-sensing method senses the body diode conduction time of the current cycle and adjusts the SR on-time for the next cycle. A configurable body diode conduction detection window is introduced to determine whether the SR on-time is too long or too short. The body diode conduction time can be regulated to a desired length. There is also a negative current prevention mechanism to improve system robustness. Compared with conventional solutions, the benefits of the proposed method are:

  • Achieve high efficiency in a wider load range
  • Automatically compensate for power stage component parameter variations, no calibration required
  • Large signal detection, easy layout, no parasitic concern
  • No minimum on/off time or blanking time constraints
  • Better noise immunity compared with competitive solutions
  • Good performance for both low-current and high-current applications with MOSFETs in parallel

Body diode conduction sensing-based adaptive SR control
 
Desired SR operation

The desired SR operation is different in a variety of LLC operation modes. As shown in Figure 2a–2b, at below or equal to resonant frequency, the SR turn-on edge follows closely to the primary side turn-on edge. The SR turn-off edge is then determined by approximately half of the resonant period. At above resonant frequency (Figure 2c), the SR turn-on edge is delayed versus the primary side turn-off edge. The SR pulse width is always equal to approximately half of the switching period. Therefore, the turn-off edge of the SR may go past that of the primary side.

 

Figure 2: Desired synchronous rectifier operations in a half-bridge LLC converter
 
Body diode conduction detection
 
The body diode conduction detector is a comparator with a –150 mV threshold. When body diode conducts, the drain-to-source voltage of the MOSFET, it is usually around -0.7V. This is typically below the threshold, and the comparator outputs are low. Otherwise, the comparator output is high. The body diode cannot be conducting when SR is on. It only happens when SR is off. To avoid any false noise trip on the comparator when SR is on, the comparator output is always pulled high when the SR gate drive signal is high.

Figure 3: Body diode conduction detection – (a) and (b)

 
Figure 3 shows two different cases for how the body diode of the SR MOSFET conducts: a) MOSFET turns off too early, positive current flows; body diode conducts right after SR turns off; b) MOSFET turns off too late, negative current flows; drain-to-source voltage shoots up first, then body diode conducts.

In both cases, the SR on-time should be adjusted in different directions. The digital controller must be able to tell them apart to avoid adjusting in the wrong direction. A detection window is generated for this purpose. The detection window starts right after the SR gate drive turns off. The length of the detection window can be configured based on the delay in the circuit.
 
If during this window the detected comparator is low, this indicates that SR is turning off too early. If during the detection window no comparator low is detected, this indicates that the SR is turning off too late. Based on this information, the digital controller adjusts the SR on-time of the next switching cycle.
 
Turn-on and turn-off edge optimization
 
In the proposed method, the digital controller outputs SR gate drive signals based on the SR clamp method mentioned earlier. This signal, called IN, has a rising edge and a fixed dead time with the primary side gate drive signal. The turn-off edge of IN moves together with the primary side gate drive signal at equal to or above resonant frequency. At lower than resonant frequency, the falling edge of IN is fixed to generate a fixed SR pulse width.
 
The output of the diode conduction detection comparator is called DCT, which is low when the body diode conducts.

The actual SR gate signal is called OUT, which can be considered as the SR gate driver IC output.
 
The rising edge of the OUT signal is determined by both the digital controller output IN, and the DCT comparator output DCT. The OUT signal can only be high when IN is high. If at IN rising edge, DCT is already low, turn on the gate driver output immediately. If at IN rising edge, and DCT is still high, turn on the gate driver output as soon as the DCT falling edge is received.

Figure 4: Turn-on edge optimization
 
On the SR gate driver and DCT detector side, the falling edge of OUT is determined by IN only. The gate is turned off immediately at the IN falling edge. Optimizing the SR turn-off edge is done by the digital controller. The digital controller uses a high-resolution digital counter to determine how long DCT is low during the detection window. If during the detection window, the DCT low time is too short, the falling edge of IN will be moved backward in the next cycle. If during the detection window, DCT low time is too long, the falling edge of IN will be moved forward in the next cycle.

Figure 4 shows the critical signals mentioned in this section.
 
Negative current prevention
 
When the SR pulse is on for too long (Figure 5), the drain-to-source voltage shoots up. The upper waveform shows the SR current. The lower waveform shows the SR drain-to-source voltage. The black segment is when SR is on, the current keeps dropping and goes negative. The drain-to-source voltage keeps a low voltage close to 0V. The red section shows that when SR is turned off, the negative current has to reset. This causes the capacitance across the drain and source terminal to charge up, and the drain-to-source voltage goes up. The green section shows that when the negative current reset process is completed, the body diode of the MOSFET conducts again briefly.

 
Figure 5: LLC converter SR drain-to-source voltage shoot up when there is negative current flow

To detect negative current, the same detection window and body diode conduction detector described earlier can be used. When there is no body diode conduction during the detection window, negative current may have occurred and the digital controller takes an action to protect the system from damage.

Hardware implementation

To prove the proposed method, a digital controller is implemented in silicon to control a 360W LLC resonant converter. A gate driver IC with the DCT detector is developed as well.
 
Figure 6 shows how the DCT is measured and how the digital controller takes action to adjust the SR on time. This figure shows that a DCT detection window is determined by a DCT blanking time register and a DCT detection window length register.
 

 

Figure 6: Hardware implementation – digital controller

 

Figure 7: Hardware implementation – SR gate driver and the DCT detector
 

The DCT signal is only detected during the narrow detection window (Figure 7). The signal outside of the detection window is ignored. Therefore, good noise immunity can be achieved comparing with the conventional method mentioned in the first section.
 
In Figure 7, the system block diagram of the SR gate driver together with the DCT detector is illustrated. As can be seen, the turn-on edge optimization can be implemented in a few basic digital building blocks.
 
Experimental results

Turn-on and turn-off edge optimization

Figure 8 shows the turn-off edge optimization waveforms. The upper left image shows that the SR on-time is too long. The lower left figure shows that the SR on-time is too short. After optimization, both conditions get corrected and a very small body diode conduction time (control target) is maintained.

 

Figure 8: Turn-off edge optimization
 
Figure 9 shows the turn-on edge optimization waveforms. The upper left figure shows when the SR is turned on too late. The lower left figure shows when the SR is turned on too early. After optimization, both conditions are corrected. A very small dead time can be maintained at the gate driver turn-on edge.

Figure 9: Turn-on edge optimization
 
Efficiency improvement
 
Compared with conventional digital control, the proposed method can improve the system efficiency by up to 0.8%. The top diagram in Figure 10 shows efficiency improvements in different input voltages. At 340V input, the efficiency improvement is the most significant. This is because in 340V, the SR clamp method no longer works well, and large body diode conduction time exists. The proposed auto-tune method benefits the most at these points. The bottom diagram in Figure 10 shows three test conditions, all with 380V input voltage. This method helps more when the resonant tank error goes bigger.

Figure 10: Efficiency improvements
 
Conclusion

 

The proposed adaptive synchronous rectification method overcomes the drawbacks of various conventional analog and digital SR control methods, resulting in higher system efficiency and improved robustness. With body diode conduction sensing, both the turn-on edge and turn-off edge of the SRs are optimized. Compared to the Rdson sensing method, the proposed method senses a large signal that doesn’t change much with layout and load current. This makes the hardware design much easier. Compared with the SR pulse width clamp method, the proposed method eliminates the need of resonant tank calibration in production. Examples of devices with this silicon implementation method are the digital power controller UCD3138A and the companion SR gate driver UCD7138.
 
References

 W. Feng, FC. Lee, P. Mattavelli, and D. Huang, “A Universal Adaptive Driving Scheme for Synchronous Rectification in LLC Resonant Converters,” IEEE Transactions on Power Electronics, vol. 27, No.. 8, August 2012
 
UCD3138A datasheet
UCD7138 datasheet
 


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