Leading-edge modulation improves power-supply efficiency in PFC designs

Technology News |
By eeNews Europe


   A power supply which uses a two-stage power system is usually required to meet the 80 Plus initiative power factor (PF) requirements and EN61000-3-2 harmonic current requirements, as follows:

•A power factor corrected (PFC) boost pre-regulator (Stage 1) to shape the input current and provide high PF.

•Since the PFC boost voltage is quite high, it requires a second stage (Stage 2) to step down the high boost voltage to a usable output level.

   The main problem with this is that adding a second stage to the front of the power converter makes for a less-efficient power supply. This can make it more difficult to meet 80 Plus initiative high-efficiency requirements.

   To try to recover some of the losses incurred by adding a PFC front stage to an offline power converter, some designers use many different PFC topologies, such as a PFC boost follower to reduce switching losses and/or interleaved PFC to reduce conduction losses.

   Another technique for reducing losses is to design one stage (Stage 1) using leading-edge pulse-width modulation (PWM) and Stage 2 using traditional trailing-edge modulation. This article discusses what leading edge modulation is and how it can improve the efficiency by reducing the high-frequency RMS current in the boost capacitor (IC).


Figure 1. Two-stage off-line power converter with PFC

(click here for enlarged image).

Trailing-edge and leading-edge PWM

   A trailing-edge PWM comparator controls the power-converter duty cycle (D) by comparing a sawtooth voltage waveform (OSC) with an error voltage (ERR). Generally, the error voltage is controlled by a feedback operational amplifier (op amp). In a trailing-edge PWM, generally the OSC pin is fed to the negative input of PWM comparator while the error voltage is fed to the non-inverting input of the PWM comparator.

   The output of the PWM comparator is used to control the gate of the FET of the power converter (QA). The gate drive turn-on signal is synchronized with valley of the OSC signal. In this configuration the trailing-edge of the FET gate drive is modulated to achieve the power converters duty cycle (D). The trailing edge is when the FET is being turned off (Figure 1).

   Note that in PWM controllers, an intentional dead time is added before every PWM cycle that turns off the power stages switch before the beginning of every PWM cycle. A dead time must be given in order to prevent 100 percent duty cycle, preventing magnetic saturation. Note for simplicity that dead time is not presented in Figure 1.


Figure 2: Trailing-edge and leading-edge PWM

(click here for enlarged image).

   Leading-edge modulation PWM is slightly different than trailing-edge modulation. The OSC signal is fed to the non-inverting PWM comparator input, while the error voltage is fed into the inverting pin. The FETs (QB) turnoff is synchronized with the OSC peak voltage and the leading edge when the FET turns on is modulated to achieve duty cycle (Figure 2).

Benefits of using leading-edge/trailing-edge modulation together

   First, let’s study the PFC boost capacitor current (IC) when trailing-edge modulation is used to control both FETs Q1 and Q2 (Case A, Figure 3) of the power stage presented in Figure 1. Note the PFC control voltage (ERR1) is compared to the oscillator ramp (OSC) to control the on and off time for the PFC FET (Q1). The DC/DC converter (Stage 2) control voltage (ERR2) is compared to the oscillator ramp as well to control FET Q2’s on and off time.

   Under normal operation at the beginning of the oscillator period, both FETs are on at the same time (t1, Case A). During this time the PFC boost capacitor (CBOOST) has to support all of the current going into the second power stage (IT1). In this configuration, during the FET switching periods, there is a time (t2, Case A) when FET Q1 is on and Q2 is off where the PFC boost inductor (L1) is being energized and the primary of power Stage 2 is not demanding any current. At this time there is no current (IC) going into the boost capacitor. All of the inductor current is passing through transistor Q1.

   There is also a time when both FETs Q1 and Q2 are off. At this time CBOOST conducts all of the boost inductor current passing through diode D1 (ID1). Note that Figure 3 is a snap shot in time. Under normal operation the duty cycle of Stage 1 varies with line voltage to maintain the PFC boost voltage. The duty cycle of power Stage 2 remains constant under normal operation, since the input/output voltages are fixed.

   Second, let’s study the affect on the boost capacitor current (IC) by controlling FET Q1 with leading-edge modulation and FET Q2 with trailing edge modulation (Case B, Figure 3). In this evaluation, both FETs Q1 and Q2 have the same on time and duty cycle as presented in Case A.

   In this configuration FET Q2 turns on at the oscillator valley and turns off based on the PWM comparator voltage levels. FET Q1 turns on based on the leading-edge PWM comparator and turns off at the oscillator peak. Staggering the FET’s initial turn on by using a leading-edge/trailing-edge PWM modulation combination reduces the amount of time when both FETs Q1 and Q2 are on at the same time (t1, Case B), compared to both stages using leading-edge modulation.

   Similar to Case A, there is a time (t2) where Q1 is on and Q2 is off, and no current is going into or out of the boost capacitor (IC). There is also a time interval (t3, Case B) where both FETs are off and ID1 needs to be absorbed by CBOOST. In Case B there is a time where FET Q2 is on and Q1 is off. At this time the current going into the boost capacitance is ID1 less IT1 (t4, Case B).

   This technique of using leading-edge/trailing-edge modulation control reduces the amount of time where FETs QA and QB are on at the same time, compared to both stages using trailing-edge modulation control. This results in lower boost capacitor RMS current (IC) as shown in Figure 3.

   Leading-edge/trailing-edge modulation in this configuration can have 30 percent less boost capacitor (IC) RMS current, compared to controlling both stages using trailing-edge modulation (Reference 1). This reduction in RMS current in the boost capacitor reduces boost capacitor ESR losses, increasing overall system efficiency.


Figure 3: Comparison of modulation schemes

(click here for enlarged image).

Lab evaluation

   To show how using leading-edge/trailing-edge modulation reduces the RMS current in the boost capacitor, a 100W off-line power converter is modified to use both trailing-edge/trailing-edge modulation and leading-edge/trailing-edge modulation schemes. A snapshot of the boost capacitor current (IC) and the FET’s gate voltage are taken under the same load and line conditions with an oscilloscope and current probe.

    Note that all settings on the current probe and oscilloscope are the same; refer to Figure 4 for a snapshot of both conditions. Ch1 is the Q1 gate voltage, while CH2 is the Q2 gate voltage, and CH3 is the boost capacitor RMS current. These waveforms are very similar to the ideal waveforms presented in Figure 3. Case B has less boost capacitance current compared to Case A.


Figure 4: Modulation schemes compared

(click here for enlarged image).


   There are many techniques for designing off-line power converters with power factor correction. The most popular to meet EN61000-3-2 harmonic requirements and/or 80 Plus requirements is a two-stage power converter . Using a leading-edge PWM control for the PFC stage (Stage 1) and trailing-edge PWM modulation to control the DC/DC power stage (Stage 2) can reduce boost-capacitor RMS current. In turn, it reduces the boost capacitance conduction losses, making the overall design more efficient compared to controlling both stages with trailing-edge PWM modulation.


1. “BiMOS Power Factor Regular,” Datasheet, SLUS577C, Texas Instruments, March 2009, page 18

About the author

Michael O’Loughlin is a Senior Applications Engineer with the Power Supply Control Products group at Texas Instruments. He specializes in offline and isolated power supply design and has authored numerous articles on power factor correction and power supply design related topics. Michael received his Bachelor of Science degree from the University of Massachusetts. He can be reached at


Linked Articles
eeNews Power