Lattice and Flexibilis unveils first FPGA Ethernet Switch IP cores with HSR (IEC 62439-3) protocol support

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By eeNews Europe

Data forwarding and classification inside the switch is based on MAC address information in the packets and the prioritization scheme. Quality of service is supported with up to four queues per port. The Ethernet switch IP core is available in five versions that vary in their number of ports and functionality:      

  • High Availability Seamless Redundancy QuadBox FES   
  • High Availability Seamless Redundancy RedBox FES   
  • 8-port FES 
  • 4-port FES 
  • 3-port FES      

The FES with HSR IP cores enables designers of substation automation and industrial networking applications to immediately and confidently apply the emerging High Availability Seamless Redundancy (HSR) protocol using LatticeECP3 FPGAs.  The IEC protocol (IEC62439-3) provides cost effective redundancy with no single point of failure and zero recovery time in case of failure. 

The protocol is applicable across a range of applications that demand high availability and sub-microsecond accuracy. 

Target applications include smart grid substation automation and networked industrial automation gear, as well as in high availability network equipment.     

The FES IP cores are equipped with IEEE 1588 version 2 end-to-end transparent switch functionality, which significantly improves the ability to resist the degradation of clock information quality in larger networks. The ability is critical in meeting the strict quality of service (QoS) requirements in wireless backhaul, wireline access, datacenter bridging and industrial Ethernet application. This feature makes the FES IP cores suitable for applications such as microwave backhaul routers, cell side routers and industrial automation products.     

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Visit Lattice Semiconductor at


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