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Latest radiation hardened power management products solve new design challenges

Technology News |
By eeNews Europe

The space industry has an increasing demand for advanced power management products that can survive harsh radiation environments and still provide “commercial-like” high performance capability. The Low Dropout Regulator (LDO) is often the device of choice when the load requirements are under 2Amps or when an easy to implement solution is desired. High sensitivity RF amplifier applications also dictate the use of LDOs over a switching regulator due to output noise performance capabilities. A switching regulator is a great fit when stepping down to a low voltage or when the current requirement exceeds 2A, necessitating a more efficient solution. With the adoption of next generation core processing solutions for satellite applications, such as FPGAs, the total power requirements and regulation tolerances are challenging designers to look beyond what is available today. For example, load current requirements are going up as core voltages are going down and voltage tolerances are being reduced from +/-10 percent to +/-5 percent in some cases. A power supply to meet this +/-5 percent tolerance — with an output voltage accuracy over static and dynamic operation, temperature range, load transient response and single event transient performance – requires a next generation solution. For example, the Virtex V FPGA uses a core voltage of 1.0V +/-5 percent and an auxiliary supply voltage of 2.5V +/-5 percent.


Figure 1: A typical power system arrangement for an FPGA

The tight regulation specification required by FPGAs requires that the tolerances of the band gap reference of a switching regulator be accurate over the entire input and output operating voltage. Using a proportional to absolute temperature (PTAT) band gap and on-chip trimming can achieve this goal in monolithic power devices. The overall tolerance of the regulator is based on the device band gap accuracy, external setting resistor tolerances, and the effects of operating over the desired temperature range. If the initial accuracy of the device is fixed, for example +/-1.5 percent over temperature, the tolerance of the external resistors will be additive to this error term. For example, using +/-1 percent external resistors, will set the output voltage set point divider tolerance at +/-2.0 percent. Both of these add up to a total regulation error of +/-3.5 percent worst case. The core voltage of FPGAs & microprocessors now require the power regulator to regulate down to a typical output voltage of 1V +/-5 percent while including factors such as SET, load transient, line and load variation.

The satellite power system environment has to adapt itself to ever increasing clock rates, thereby demanding more power along with rapidly changing loads. This requires that the regulator have a good transient response, with a typical dI/dt of 10A/µs for a 0-percent to 100-percent load step. During these step load conditions, a maximum output voltage excursion +/-5 percent is desirable. Exceeding any of the FPGA maximum supply voltage limits during the load step can result in immediate or latent damage to the expensive FPGA, affecting system reliability. LDOs are the device of choice for loads of up to 2A, and integrated MOSFET switching regulators can be used for loads in the range of 2A to 12A. These devices have large energy storage capacitors on the output pin which impose a huge burden on the power bus during the power up cycle, causing bus load currents to increase momentarily by as much as an order magnitude. The use of the programmable soft start function available in these next generation devices will help keep the startup load current within a predetermined limit and avoid over designing of the power bus. The ability to build an intelligent power solution that can be controlled / sequenced from a microprocessor sub-system is desirable too. This is achieved by the enable and power good (PGOOD) functions. The enable function also serves the purpose of putting the regulator into a low quiescent power state. A programmable over current limit helps limit the energy dumped into a short-circuited load. Also, with switching frequency capability up to 1MHz, the external inductor and capacitors can be reduced in size, saving valuable board space. All of the above comes with minimal to no additional external components, unlike a discrete solution, which again minimizes the power solutions footprint and increases overall system reliability.

LDO designs commonly use a PMOS device as a pass element, which enables operation at a minimum input voltage of 2.2V typical and at lower quiescent ground current as a result of simpler drive circuits. Additionally, LDO devices provide very low ON resistance and dropout voltage. Typical dropout voltages seen with a device such as the ISL75051SRH are 65mV at 1A load current and 225mV at 3A. The low dropout and ground current help to reduce power consumption in satellite power systems, lower the temperature rise of the regulator, and result in cooler system operation.

Single event effects (SEE) include a range of destructive and nondestructive effects in the energetic proton and heavy ion environments commonly encountered in space. Destructive effects include single event burnout (SEB), in which the device suffers permanent damage. In single event latch up (SEL), parasitic PNPN structures internal to the chip are triggered and the device will enter a latch up condition causing noticeably higher supply current. If the SEL condition can be reset by recycling the power source, returning the supply current to normal, it is called a soft latch. Single event transient (SET) is a nondestructive (soft) error, which results in a short duration increase or decrease in the device’s output voltage. The magnitude of the SET pulse is an important parameter, as exceeding +/-5 percent power supply voltage tolerance of an FPGA can result in immediate destructive damage to the device, and SET performance is a major consideration in power management applications.

SEE mitigation design techniques
SEE mitigation calls for design techniques like redundancy and special device cell layout in order to mitigate the momentary deviations in the output caused by ion strikes. FPGA power requirements dictate that the VOUT single event transient deviation be limited to less that +/-5 percent, typically at an ion linear energy transfer (LET) value of 86 MeV•cm²/mg. In addition, these hardened devices are designed to be tolerant to the total ionizing dose environment, which in space applications typically consists of electrons and protons. All parameters of the device specification table are guaranteed to remain within the min/max limits specified in the Standard Microcircuit Drawing (SMD) up to the specified dose, typically 100 krad(Si) for the high dose rate of 50 – 300rad(Si)/s and 50krad(Si) for the low dose rate of 0.01rad(Si)/s, with the lower dose rate more accurately reflecting actual space conditions. The commercial equivalents on the other hand are not specified for these radiation environments, and will experience permanent damage, parameter shifts or potentially destructive output voltage transients.


Figure 2a: SET AT LET 86 MeV.cm²/mg VIN = 4.0V, VOUT=1.8V, IOUT=0.1A


Figure 2b: SET AT LET 86 MeV.cm²/mg AT VIN = 4.0V, VOUT=1.8V, IOUT=1.0A

Figure 2: Typical SET captures for the radiation hardened ISL75051SRH LDO at
light and heavy load.

Samples were tested at an ion LET of 86 MeV•cm²/mg at an input voltage of 4.0V and an output voltage of 1.8V. The left traces are for an output current of 0.1A and the right ones are for 1.0A. The lower (blue) traces show a 40mV increase of the output voltage for the 0.1A case and a 30mV increase for the 1.0A case, which represents approximately 2 percent of the output voltage.

With a point of load regulator that is specifically designed and qualified for the space environment, these challenges can be met head on. For example, the above transient plots above show that the single event transients (SET) observed under beam are well within the +/-5 percent requirement. Fast transient response and high slew rate require compensated wide bandwidth closed loop feedback, which will remain stable over the defined COUT and load range. To some degree this response time defines the recovery time from SEE as well, so a fast system is likely to show a narrow transient lasting for less than 5µs when compared to a slow system which can take a couple of milliseconds to recover. SET performance of at least less than +/-5 percent is critical to a space environment power supply, otherwise it will be impossible to meet the overall +/-5 percent FPGA voltage tolerance.

There are various reasons why designers may prefer a hybrid module or discrete component solution over a monolithic integrated circuit solution. A lot of it is driven by application specific reasons such as power dissipation requirements or layout considerations. A highly integrated hybrid is typically used when board space is a major constraint, and a discrete solution may be attractive when output power requirements are high. A monolithic IC solution is a good balance between these two alternative power supply designs. In a monolithic voltage regulator, the power MOSFETs and drivers are integrated onto the silicon. This typically reduces the overall power management solution footprint versus discrete solutions and improves the overall reliability of the system as there are now fewer solder joints that can fail over time. Despite the FETs being on silicon, IC devices can still handle a significant amount of power. For example, the new ISL70002SEH point of load (POL) regulator can output > 55 watts at a junction temperature of 150oC. This allows the designer to use a compact solution versus a discrete solution and still meet most of the load power requirements. Since hybrid solutions tend to integrate most components within the same large enclosure, the user does not have very many options when designing in the hybrid. With fewer external components needed for the integrated POL versus a discrete solution, more time can be focused on the core portion of the system design and less on procuring components or working on the power supply design and layout.

The next generation monolithic power management components being released today are critical solutions for space power designers’ needs for low power dissipation and weight, which are very critical in satellite systems with ever shrinking payload size. Their simplicity greatly reduces the design cycle time, while still providing “commercial-like” features liked, tight tolerances, good stability and intelligent control. The smaller footprint also permits mounting the voltage regulator closer to the actual application printed wired board (PWB) as compared to discrete / hybrid solutions, where the power solution may be on an adjacent power board or at a distance.

About the authors:
Josh Broline is a Lead Marketing Engineer under Intersil’s High Reliability products group responsible for the Space & Harsh Environment product lines. He has 10 years of service with Intersil, the first 5 years as a Product Engineer and the last 5 as a marketing engineer responsible for various product lines.  Josh has a BSEE from University of Central Florida and an MBA from Florida Institute of Technology.

Theju Bernard is Principal Applications Engineer working in the High Reliability products group at Intersil Corporation. He is responsible for the new product development in the Space and Harsh environment arena. He has 29 years of industrial experience of which the last eight have been with Intersil. He served as Application Engineer in the Consumer group for three years and five years to date as Application Engineer in the High Reliability group. Theju holds a BSEE from the University of Mysore, India.

Nick van Vonno is a Principal Engineer in Intersil’s High Reliability products group. He has 42 years of service with Intersil and its predecessors in a number of technical and management posts. He is currently responsible for radiation effects research, customer support and technology development for the product line. Nick has a BSEE from the University of Florida and is a Senior Member of IEEE. He received the IEEE Radiation Effects Award in 2009.


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