JEDEC udpates universal flash storage standard for lower power, faster performance
Specifically tailored for mobile applications and computing systems requiring high performance and low power consumption, the new UFS v1.1 standard is an update to the v1.0 standard published in 2011, incorporating feedback from industry UFS technology implementers.
JESD220A Universal Flash Storage v1.1 contains important amendments and references to the latest related MIPI Alliance specifications, and may be downloaded free of charge from the JEDEC website: https://www.jedec.org/standards-documents/results/jesd220a.
JEDEC has also published a complementary standard, JESD223A UFS Host Controller Interface (HCI) v1.1. JESD223A defines a standard host controller interface on which system designers can create a common host controller software driver layer to work with UFS host controller hardware from different manufacturers. The HCI functionality also enables higher performance and power efficiency by minimizing the involvement of the host processor in the operation of the Flash storage subsystem. JESD223A Universal Flash Storage Host Controller Interface v1.1 may also be downloaded free of charge: https://www.jedec.org/standards-documents/results/jesd223a.
To allow for easy transition from e·MMC technology, UFS v1.1 has implemented functionality that are compatible with e·MMC v4.51 command protocol improvements such as Context ID (grouping different memory transactions under a single ID so the device can understand that they are related), and Data Tag (tagging specific write transactions so they can be prioritized and targeted to a memory region with higher performance and better reliability).
To achieve the highest performance and most power efficient data transport, JEDEC UFS aligns with industry–leading specifications from the MIPI Alliance to form its Interconnect Layer. This collaboration continues with UFS v1.1, which supports the M-PHYTM and UniProSM specifications. Recently published, the newest UniPro specification defines a universal chip-to-chip data transport protocol, providing a common tunnel for higher-level protocols. The updated M-PHY interface is designed as the primary physical interface (PHY layer) for the UniPro specification, and is a high speed serial interface. The next generation M-PHY reaches 2.9 gigabits per second (Gbps) per lane with up-scalability to 5.8Gbps per lane.
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