MENU

IEEE 2416 power modeling standard approved

Technology News |
By Nick Flaherty

IEEE 2416 complements the IEEE 1801-2018 Standard for the Design and Verification of Low-Power, Energy-Aware Electronic Systems. It provides a rich set of power modeling semantics enabling system designers to model entire systems with great flexibility. It also supports power modeling from abstract design description all the way to gate level implementation providing data consistency from earliest architectural explorations to final power verification.

“We view IEEE 2416 as a major step forward for low power design,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE2416 and the Si2 UPM Working Groups.

“Energy-aware, system-level design can be a challenging task,” said John Biggs, chair of the IEEE P1801 Working Group, and distinguished engineer and co-founder of Arm. “With this new standard, designers will be better enabled by having access to semiconductor IP delivered with both IEEE 1801 power state models and IEEE 2416 power data models.”

The standard is based around the Unified Power Model (UPM) developed by the Silicon Integration Initiative (Si2) along with major contributions from IBM and GLOBALFOUNDRIES (GF). The UPM is a result of the Si2 OpenStandards Coalition, an R&D incubator which rapidly seeds and prototypes potential new EDA software tool interoperability standards.

“The foundation of the EEE 2416-2019 standard originated in IBM and has been successfully used in power sign-off of several generations and families of IBM microprocessors,” said Dhanwada. “Concepts like multi-level, state based modeling and efficient, expressive semantics in IEEE 2416-2019 support constructing accurate and standardized power models for IP blocks. This enables SoC designs to be energy efficient from the ground up, a key reason companies will use 2416-2019 to upgrade modeling, analysis and sign-off flows,” he said.


For design automation groups, UPM provides an industry-standard format for both internal and external IP. This common format saves resources and time as there is no need to support or translate external proprietary formats. UPM also reduces reliance on internal proprietary formats, a long-standing design obsolescence trap.

The model uses Process, Voltage, and Temperature as independent proxies for power. This PVT independence enables the late binding of PVT conditions at simulation run time, enabling power analysis at various PVT corners without requiring new libraries. Multi-level models provide multiple model views, or interfaces, to access the same power data. With multi-level construction, a single model provides consistent data for both system-level abstract simulations and bit-level simulations with RTL or gates.

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF.  “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

A prototype power tool, upmPowerCalc, was built to prove the new concepts from end-to-end, both accelerating the delivery of a ready-to-implement standard and providing OpenStandards members with tools to aid in their own implementation.

The Si2 work was supported by the UPM Working Group consisting of ANSYS, IBM, Intel, Cadence, Entasys, and EDA start up Thrace Systems.

“The target of this development and subsequent standardization was an efficient and flexible mechanism for the specification and interchange of consistent power models throughout a project’s lifetime, from system design to manufacturing, especially for IP blocks and chiplets,” said Jerry Frenkil, director of OpenStandards at Si2. “This work led to significant advances in power modeling, including contributor and multi-level modeling, both of which are included in the 2416-2019 standard.”

“These advancements, along with UPM’s semantic expressiveness, deliver multiple benefits for design organizations” said Frenkil. “System architects and SoC designers can model entire systems at a variety of PVT points with great flexibility. Power can be modeled in UPM using scalars, tables, expressions, and contributors, as well as expressions referencing contributors.”

There are also benefits for IP developers. The use of power contributors reduces the number of  models and libraries that are needed and the models are abstract black boxes – functionality cannot be reverse-engineered from the power models.

Model interoperability and consistency with the IEEE1801 standard were identified early on as key goals in support of increasing emphasis on system level design. “IEEE2416 provides a standardized interoperable system-level power model that is an essential piece of the foundation of an emerging industry-scale chiplet ecosystem,” said Ramune Nagisetty, senior principal engineer and director of Process and Product Integration at Intel Corporation.

Thrace Systems is planning to add IEEE 2416 support to its products. “IEEE 2416 is an important new standard. Its rich modeling semantics provide our power analysis platform with the solid infrastructure needed for comprehensive system level analysis,” said David Ratchkov, founder and CEO at Thrace.

www.si2.org


Share:

Linked Articles
eeNews Power
10s