How to get 500W in an eighth-brick converter with GaN, part 1
DC-DC “brick” converters are familiar to many engineers, and have wide usage in telecommunications, networking, data centers, and many other applications. This is due in large part to adoption of a common footprint defined by the Distributed-power Open Standards Alliance (DOSA) and generally accepted input/output voltage ranges . These converters provide isolation and voltage step-down, and have become increasingly sophisticated, with features that enable advanced system optimization and control. They often reside on motherboards where they drive point-of-load converters for processors and memory. Increasing data processing throughput requires more power, more board real estate, or both. Power processing is considered a cost, and information processing a source of profit. Hence, there is continuous pressure to increase power density. However, as the technology has matured, improvements in basic power conversion capability, that is, power density and efficiency, have slowed down to a crawl.
All is not lost, however, as GaN power semiconductors give basic power converter technology a much-needed shot in the arm. GaN transistors already show large improvements over similarly rated silicon devices . This article shows that these improvements are more than good looking datasheets via a design example that demonstrates a complete eight-brick converter design with eGaN FETs and real test results. This converter can deliver more than 500 W using a conventional transformer-isolated, hard-switched, PWM regulated design. It represents a new starting point that can be achieved with GaN – and with room to grow.
This article will appear in two parts. Part 1 covers brick technology, a comparison of eGaN FETs to silicon MOSFETS, a basic overview of the GaN-based eighth-brick design, and experimental results. Part 2 gives a detailed design overview to show how to get the most out of eGaN FETs, along with a number of ways that the design could be improved.
At the 100 W to 1 kW level, quarter-brick (Q-brick) and eighth-brick (E-brick) DOSA-compliant converters are commonly used to convert a nominal 48V backplane to a nominal 12V motherboard distribution bus. The main trend has been towards higher power density. Another trend has been an improvement in the regulation of the input bus, which allows a reduced converter input voltage range. This enables further improvement in power density, and in some cases even unregulated converters. For the Q-brick format, this has led to output powers in the 800W range, with output currents approaching 80 A .
The E-brick format has not kept pace with the Q-brick. The need for higher power is felt here as well, but the smaller format poses additional challenges. The controls, the gate drives, isolation and spacing requirements, and PCB manufacturing tolerances are nearly the same for both E- and Q-bricks. Since the volume required for this overhead is largely independent of converter size, this places a greater challenge for smaller converters. GaN technology is uniquely suited to address this challenge.
The introduction of commercially available low-voltage GaN FETs dramatically increases the achievable power levels and efficiencies in brick converters. The fourth generation of eGaN FETs have figures of merit (FOMs) up to 14× better than silicon, breaking down a major barrier towards much greater converter power density. This article describes the development of a fully regulated, isolated E-brick converter using eGaN FETs to demonstrate that GaN technology can far exceed the performance of the best silicon MOSFETs [4, 5]. This converter is capable of over 500 W and has a peak efficiency of 96.7%. Full details on the converter, including schematics, bill of materials (BOM) and Gerber files can be found on EPC’s website . In this article, we cover the following aspects of this design:
- Existing E-brick technology
- Design goals
- Benefits of 4th-generation eGaN FETs
- Converter design
- Experimental results
- Potential Improvements
Existing E-brick technology
A commercial example of a high-performance E-brick converter is shown in Figure 1. Typical E-brick converters are used as integrated bus converters which convert a nominal input voltage range of 36-75V to an output voltage in the range of approximately 9.6V to 13V. The standard footprint and pinout mean that these converters have been widely adopted for telecom and data center applications.
Figure 1 An example of a high-performance commercial E-brick converter.
Table 1 shows four examples of state-of-the-art commercially available E-brick converters that use silicon MOSFETs [7, 8, 9, 10]. These examples have the highest power rating presently available, up to 320 W. Each vendor rates power and efficiency under different conditions, so this is an inexact comparison. As one of the methods to achieve the higher power density, the input voltage range has been reduced from the previous generation of E-bricks, and in some cases the output voltage lowered as well.
Table 1 Main specifications for state-of-the-art commercially available E-brick converters.
These converters represent decades of progress and experience with silicon MOSFET-based design, and a great deal of effort is required for relatively small improvements. With the advent of eGaN FETs, it is now possible to leapfrog silicon-based designs.
The eGaN FET-based E-brick converter was developed with the following design goals:
- 500W output at 12V (42 A output)
- 48V to 60V input range (52V nominal)
- Fully regulated
- > 96% efficient at full load
- DOSA-compliant footprint
- Off-the-shelf parts
The output power was chosen to demonstrate a large step change in output power rather than the incremental changes that are the norm for a long-established technology. The chosen input voltage range is narrow, similar to most of the highest power converters. Requirements include full regulation and isolation, along with a DOSA-compliant footprint. Thermal limitations demand an efficiency > 96% at the full load current. Finally, the converter uses only off-the-shelf components, so that it is clear that the benefits are derived from the use of eGaN FETs.
Benefits of 4th-generation eGaN FETs
eGaN FETs have many benefits over silicon MOSFETs that make them particularly well suited to E-brick applications. These include small size, reduced gate charge, lower parasitic capacitances and inductances, lower gate drive voltage, zero reverse recovery, lower specific RDS(on), and faster switching . The FETs chosen for the E-brick demo board are the 4th generation regular pitch eGaN FETs from EPC, shown in Table 2. The table also shows the relaxed pitch FETs, which are targeted towards designs that still require wider tolerance PCB manufacturing processes. These FETs are available in a range of voltages from 30V to 200V. As can be seen in the table, this selection of the available large-area FETs have very low RDS(on) values, a requirement for intermediate bus converters (IBCs).
Table 2 Examples of large-die eGaN FET selection suitable for brick-type converters.
We start by comparing eGaN FETs with available state-of-the-art silicon MOSFET candidates for the E-brick application. We wish to compare parts with breakdown voltages of 80V (primary side) and 60V (secondary side). These are typical values for the application. A typical implementation with silicon MOSFETs would be four 3.3×3.3 mm PDFN primary transistors and two 5×6 mm PDFN secondary transistors. This gives a total transistor area of approximately 120 mm2 (4 primary transistors with a total of ~60 mm2 area, and two or four secondary devices with a total of ~60 mm2 area). The area required for magnetics, controls, and I/O means that there is no additional room for FETs. Figure 2 shows how the die size compares to a standard 5×6 mm PDFN package. We see that we can put two of the large area eGaN FETs in the same footprint of one PDFN package.
Figure 2 Relative size comparison of silicon 5×6 mm PDFN package with eGaN FET die.
For a detailed comparison, we must look at device FOMs based on the manufacturers’ datasheets [12, 13, 14, 15, 16, 17, 18, 19]. First, let’s consider the primary side FETs. In Table 3, we compare five FOMs for four state of the art transistors, including 3 silicon MOSFETs and the EPC 2021 eGaN FET. The silicon MOSFETs were chosen to be the best parts available in a 3.3 mm by 3.3 mm PDFN package as of the writing of this article, since this is the size used in a typical E-brick primary-side bridge.
Table 3 FOMs for 80V FETs. Qoss and Eoss data determined at VDS = 52V.
While five FOMs seems like a lot to compare, they all play a role, and it is instructive to break them out individually. All FOMs take into account RDS(on) and are independent of device area. We introduce two figures of merit (FOMs) that are not commonly used. The first is gate energy FOM EgRDS(on), where Eg is the energy required to switch on the FET, i.e. Eg = VGQg, where VG is the gate drive supply voltage and Qg is the gate charge. We have defined this because gate drive power is an important loss component for low RDS(on) FETs. Silicon FET data sheets can obscure this fact, as RDS(on) is almost always specified with VG = 10V, even when the part claims that the component is suitable for VG = 4.5V.
This is a substantial part of the loss budget with silicon MOSFETs. In fact, for the 500W E-brick design, if an equivalent total (primary and secondary combined) RDS(on) silicon area was used, gate power would exceed 1.5 W, almost 10% of the total loss budget. In contrast, the eGaN FET gate drive total power requirement is about 0.25W. The second new FOM is AfootprintRDS(on). This is especially important for the E-brick design, where the area is severely constrained. In fact, it may not be possible to fit enough silicon MOSFETs such that a practical converter could be built.
From Table 3, it is clear that the eGaN FETs have FOMs that are 1.3 to 14 times better than silicon parts, or, in the case of Qrr, infinitely better. For the primary side switches, the most important FOMs are EgRDS(on), AfootprintRDS(on), and EossRDS(on). Figure 3 shows a relative comparison of the data in Table 4. Each FOM is compared such that the transistor with the worst FOM in the category is scaled to unity, and the other scaled with the same factor. Looking at the relative FOMs for the silicon devices, we see that some parts are good in one category, but sacrifice performance somewhere else. This is a result of the tradeoffs MOSFET designers must make as they labor to wring more performance from silicon technology, squeezing diminishing returns from an increasing effort. The eGaN FETs show better performance in every single measure.
Figure 3 Relative FOMs for 80V FETs. Qoss and Eoss data determined at VDS = 52V.
For 60V FETs, the comparison yields the same conclusion (Table 4). In this case, we compare the EPC2020 to silicon MOSFETs in 5×6 mm PDFNs, the size most commonly used for synchronous rectifiers (SRs) on E-brick converters. In the case of the rectifiers, EgRDS(on) and AfootprintRDS(on) are obviously still important. In addition, the output charge and reverse recovery charge FOMs (QossRDS(on) and QrrRDS(on)) are also important.
Table 4 FOMs for 60V FETs. Qoss and Eoss data determined at VDS = 26 V.
Let’s consider Qrr further. The values given here are from the manufacturer data sheets, but one of the challenges with Qrr is that it is not a fixed number. It gets worse with increasing di/dt and often much worse with temperature. Its effect can be mitigated by minimizing the body diode conduction time, hence deadtime management can help, in theory. In practice, Qrr is highly variable, increases with temperature, and difficult to characterize, so that optimum deadtime is an unpredictable moving target. With eGaN FETs, Qrr is non-existent, hence diode turn-off behavior is repeatable and predictable. This allows deadtimes of <10 ns if the controller is capable. Figure 4 shows the Table 4 results graphically. Once again, we see that eGaN FETs beat silicon FETs for all five FOMs. GaN technology does not force compromises on any of the performance FOMs.
Figure 4 Relative FOMs for 60V FETs. Qoss and Eoss data determined at VDS = 26V.
The chosen approach for the converter is straightforward and conventional. Figure 5 shows a simplified schematic. The input stage consists of a full bridge of 80V EPC2021 eGaN FETs. No DC blocking capacitor is used so that the losses from such a capacitor are avoided. This drives a 4:1 fully interleaved planar transformer with a center-tapped secondary. The low resistance of the primary FETs and their fast switching and short delay times helps to minimize V∙s imbalance. Combined with careful layout and controls, this minimizes any asymmetry of the primary pulses, avoiding the need for a blocking capacitor or primary current sensing .
The output stage is a center-tapped synchronous rectifier (SR), where each of the two switches consists of two paralleled 60V EPC2020 eGaN FETs. Energy stored in the transformer leakage inductance is captured and returned to the output via an energy recovery snubber , which also limits the peak voltage on the SR FETs.
The SR drives an inductor, where DCR current sensing is used in order to minimize losses . The converter uses a fully digital controller with 1 ns resolution, which is responsible for all switch timing including the snubber FETs. We use conventional hard-switched PWM control as this is the simplest, most straightforward approach, and hence forms the best baseline case. This approach simplifies comparison of the eGaN-based converter performance of this converter to one with silicon MOSFETs. Finally, a primary switching frequency of 300 kHz was selected, double the more typical 150 kHz of a silicon converter. This halves the output inductor value, reducing the size and loss of one the biggest components in the converter.
Figure 5 Simplified schematic of E-brick converter.
Figure 6 shows top and bottom views of the completed EPC9115 E-brick demonstration board . The complete board size is larger than an E-brick to allow simple user connections for power, testing, and programming. The actual converter lies entirely within the DOSA E-brick envelope, shown by the yellow rectangle.
Figure 7 shows the efficiency versus load current for the converter at input voltages of 48V, 52V, 56V, and 60V. These data were obtained with 400 LFM (2 m/s) airflow at an ambient of 27°C, with the converter being allowed to reach thermal steady state before measurement. The converter reached a peak efficiency of 96.7% with 48V input, and, at the nominal design voltage of 52V, reaches a full load efficiency of 96.4% at a load current of 42 A. This is slightly over 500W output. Note that even at 44 A load current (526W), the efficiency exceeds 96% over the entire range of input voltage. Figure 8 shows the same data in terms of power loss.
Figure 6 Photographs of EPC9115 E-brick demo board, top and bottom.
Figure 8 Power loss versus load current for the EPC 9115 E-brick demo board. Data were obtained with 400 LFM (2 m/s) airflow at an ambient of 27°C, with the converter being allowed to reach thermal steady state before measurement.
Figure 9 is a thermal image showing the temperature distribution of the converter running at 44 A at 52V input, (526W), under the same test conditions as figures 7 and 8. The eGaN FETs have small dots of black paint to enable accurate temperature measurements, which can be seen in the thermal image. The thermal image shows the entire demo board, including the outer boundary with the additional terminals. Wherever possible, the demo board has a gap between the actual converter area and the outer PCB. Due to the minimal heat flow from the converter to the surrounding area, the eighth-brick outline is clearly seen in the thermal image.
We can see that the hottest point on the converter is the transformer core at 100°C. The next hottest point is measured on one of the secondary FETs at 91°C, well below the thermal limit of the FETs. The primary side FETs are even cooler, with a maximum temperature of only 83°C. Finally, the measured temperature of the output inductor, mounted on the bottom side, is approximately 54°C. From the data it is clear that the converter should be able to run at full rated output well above typical room temperature.
Figure 9 Thermal image of E-brick data was obtained with 400 LFM (2 m/s) airflow at an ambient of 27°C, with the converter being allowed to reach thermal steady state before measurement. Converter load current at 44 A (526W) with 52V input.
Unregulated bus converter operation
One of the primary driving forces behind the use of unregulated IBCs is the higher efficiency one can achieve by relinquishing the ability to regulate the output voltage against variation in line and load. Hence, we will examine the potential performance of the E-brick demo board operating as a DC transformer (DCX), with a few changes from the baseline design:
- The inductor was changed from a 470 nH, 0.9 mΩ DCR inductor to one specified at 210 nH, 0.3 mΩ.
- The maximum duty cycle software limit was raised from 0.980 to 0.985.
- The actual deadtime was changed from 25 ns to 15 ns.
After these changes, the converter was operated at 48Vin, with 400 LFM airflow and a 24°C ambient. The efficiency and output voltage are plotted in Figure 10. In this case, we see a peak efficiency of > 97.2 % and efficiency remains > 97% from 27 A to 52.5 A. At the maximum measured output current of 58.4 A, we measured 667 W of output power. Figure 11 shows a thermal image. We note that this extreme power level the rectifier FETs, at 106°C, approach the transformer core temperature of 108°C. The primary side devices, however, continue to run at a relatively low temperature. This is remarkable performance, and there is still room for improvement.
Figure 10 Efficiency and output voltage versus load current for modified E-brick converter running as a DCX. Data were obtained with 400 LFM (2 m/s) airflow at an ambient of 27°C, with the converter being allowed to reach thermal steady state before measurement. Maximum output power is 667W.
Figure 11 Thermal image of DCX with 400 LFM (2 m/s) airflow at thermal steady state. Data were obtained with 400 LFM (2 m/s) airflow at an ambient of 27°C, with the converter being allowed to reach thermal steady state before measurement. Output current is 58.4 A, for an output power of 667W. Output inductor temperature is 75°C.
For many years power electronics designers have been living in an era where increases in performance of 5-10% are the norm, and 20% is outstanding. We have shown that GaN can provide a 70% power density improvement in a conventional topology by taking a typical eighth-brick design and boosting the power from 300W to over 500W in a fully regulated, hard switched design. Furthermore, we’ve shown that unregulated hard-switched designs can be pushed over 650W. What’s more – there is still room to grow.
Note that we don’t just drop the transistors in. Careful attention must be paid to the layout and design to take advantage of the capabilities of the FETs. Part 2 of this article will show how to get the most out of GaN by an in-depth description of the layout, electrical performance, and losses of the eight-brick demo board. A more in-depth exploration on the use and benefits of GaN in DC-DC applications, including practical details on layout and thermal management, as well as its impact on systems and power architectures, is available in EPC’s DC-DC Conversion Handbook: A Supplement to GaN Transistors for Efficient Power Conversion .
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