Intel has developed Fully Integrated Voltage Regulators (FIVR) with embedded inductors to control the power to chiplets in 3D stacked system in package designs.
The 3D-TSV-Stacked SIP is built in a 22nm CMOS with an active silicon interposer and uses a self-trimmed, digitally controlled ON-Time Discontinuous Conduction Mode (DCM) architecture.
A team at Intel in Portland, Oregon and Chandler, Arizona developed a 10-tile buck IVR using 0.9nH-1.4nH 3D-TSV-based package-embedded inductors. This FIVR demonstrates up to 37.6% higher efficiency than a low drop out regulator (LDO).
The ten tiles achieve with flat efficiency over a 10mA-1A load range without having to communicate with each other. The FIVR tiles are interleaved to provide a stable DCM output with a 34% reduction in output ripple compared to zero interleaving.
The voltage controllers are vital for 3D packaging, which combines chiplets implemented in optimal process nodes based on the workload. This is a flexible and cost-effective to create multiple configurations but needs more complex power control.
The FIVRs are implemented on the base die in 22nm process technology with three types of TSV-friendly inductor structures that have multiple area vs. efficiency tradeoff options. These are easy to parallelize for building modular designs that can serve a wide range of different chiplets.
The three inductor structures were implemented in the ten IVR tiles in the silicon substrate to examine the tradeoffs in footprint, AC inductance (LAC), AC and DC resistance (RDC, RAC) using the TSV and package routing
The largest inductor is a Large Horizontal Solenoid (LHS). This measures 1 x 1mm and has the largest LAC/RDC and highest efficiency and is good for static workloads.
A Small Horizontal Solenoid (SHS) measures 0.32 x 0.32mm and provides moderate efficiency.
A Vertical Solenoid (VS) uses the package height for LAC and has an extremely small X-Y footprint of 1.4 x 0.1mm and provides the best transient performance.
Implementing 3D buck voltage regulators on the base die of a 3D SIP can deliver power to chiplets mounted on top. The modular FIVR design with TSV-friendly inductor structures provides flexibility in powering a variety of chiplets optimized for different uses. This offers a 37.6%-pt. efficiency improvement over LDOs and tiles with different inductor types can be ganged to obtain high-steady-state efficiency and good transient response as well as minimizing the ripple while maintaining PFM controller stability.
The design was discussed at the recent VLSI 2022 symposium.
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