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Envelope Tracking Modulator with quad power IC and FPGA control

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By eeNews Europe

Envelope tracking technology is a well-known method of improving the efficiency of RF amplifiers operating with rapidly varying signal amplitude. The voltage source in an envelope tracking system is modulated to keep the RF amplifier as close as possible to the compression, where the efficiency is at its maximum (see Figure 1).
 

 


Figure 1: Envelope tracking principle of operation (left) and reduced bandwidth version (right)

The envelope tracking technique was described by Bell Labs in 1937. The similar techniques of envelope elimination and restoration were described by L. Kahn in 1951. Yet despite its obvious advantages, practical implementations were very rare simply because of the very high requirements imposed on a modulator. It has to combine very high bandwidth (up to 100 MHz in some new systems) with high efficiency, small size, and low cost.

One of the ways to lower the bar is to reduce the bandwidth requirements. This is simple in implementation, but a significant portion of the potential efficiency improvement is lost (see Figure 2).

Figure 2: Envelope tracking with reduced bandwidth

A different approach was proposed by Gunnar Cragfors in 1981 in U.S. patent no. 4,390,846, and later by Peter Garde in U.S. patent no. 4,516,080 (see the drawing from Cragfors’ patent in Figure 3). According to these inventors, modulator should consist of two parts: a switching regulator for low bandwidth and linear regulator for high bandwidth.

Figure 3: Linear regulator (F) and switching regulator (SW) combine for high-efficiency, high-bandwidth voltage modulation in Gunnar Cragfors’ U.S. patent no. 4,390,846 (S – summing node)

While the RF amplifier can now work with full efficiency, there is a price to be paid in the cost, complexity and reduced efficiency of the modulator itself. This approach was realized in some commercial applications, but the most typical architecture is similar to the one proposed by Peter Garde, which is shown in Figure 4.
     

 

Figure 4: The most popular method for combining switching and linear regulators

While commercially feasible, the switching-linear combination is most suitable for high-end applications. For widespread applications, eliminating the burden of the linear regulator seems necessary. However, the switching frequency, which according to the rule of thumb has to be at least 10 times higher than the bandwidth, seems impossible.

The conflict between switching frequency and bandwidth can be resolved by using a multilevel converter, which can achieve a small signal bandwidth higher than the average switching frequency. This is possible because the small amplitude regulation can be realized with the switching transition of only one or two of the many subconverters, while other parts continue to deliver the “unchanged portion of the voltage.” The high / low bandwidth assignment between subconverters can be continuously rotated, resulting in an equal and moderate burden on switching devices.

The other benefit of a multilevel converter comes from the much higher frequency and lower amplitude of the switching harmonics. As a result, the output filter corner frequency can be raised so high that it does not degrade the overall bandwidth and achieving stability is much easier.

The biggest problem with using a multilevel converter for an envelope tracking application comes from the fact that existing multilevel topologies were devised for high-power, high-voltage applications. As a result, the main current path leads through a large number of power components, thus increasing conduction losses very significantly. In high-voltage applications where conduction losses are low this isn’t a problem, but for low-voltage, high-current envelope tracking applications, the resulting efficiency would be unacceptable.

Artesyn Technology developed a new type of multilevel converter designed specifically for this type of application. It consists of a large number of switching cells combined with a proprietary matching impedance network. Like in many multilevel converters, the output voltage is proportional to the number of switching cells that are on at any given time, which creates output in a stepped or staircase-like pattern. A matching impedance network has very low output impedance (about 1 nH), facilitating very high bandwidth. For ET applications, a version with 16 subconverters was chosen as adequate to keep harmonics at an acceptable level with minimum filtering. This was sufficient for a small signal bandwidth of 100 MHz and 200 W average / 1000 W peak power to an RF amplifier working with up to 40 MHz bandwidth. At the same time, the average switching frequency per phase was only about 10MHz. While still high, it is definitely within the reach of state-of-the-art silicon MOSFET technology, like the SiP2204 used for this design.

Figure 5: New multilevel converter with passive coupling network for low-voltage operation

To keep the overall efficiency above 90 %, it was necessary to add one more innovation: only a fraction of the total output power was processed through 10 MHz switching; the part associated with outputting AC voltage and AC current simultaneously. Most of the DC voltage and current was directed straight from the source to the load, entirely bypassing the switching MOSFETs with an “effective efficiency of 100 %.” Concurrently, switching voltage and current were reduced to diminish MOSFET losses. Additional improvement was achieved by the special design of the power stage in the SiP2204, which was optimized for minimal losses at light loads. With all these factors combined, the need for a linear regulator was eliminated.

The stepping output pattern of the multilevel converter creates high-frequency harmonics, which are reflected in the RF signal. The 16 subconverters used for the envelope tracking design allowed the frequency of this noise to be shifted far away from the RF channel, where it can be handled much more easily. In some applications, satisfactory operation may be achieved without any LC filter whatsoever. In other situations, more than 16 cells or subconverters with fractional amplitudes may be used instead of the filter.

A custom controller was developed in an Altera Cyclone FPGA. The initial design, similar to the one used in common multilevel converters, was based on 16 equally phase-shifted digital sawtooth waveforms and comparators. See Figure 6, which provides an example with only four phases shown to avoid cluttering the picture, but the principle for 16 phases is the same.


Figure 6: Simple realization of the PWM sequence for a low-voltage multilevel converter. The phase shift between the sawtooth and the input signal creates a variation in the step pattern

This structure can be very easily implemented in an FPGA using Simulink and DSPBuilder.

Figure 7: Simulink / DSPBuilder implementation of a 16-phase PWM generator. The initial value of each counter produces the desired phase shift

Careful analysis of the performance of the converter based on this controller revealed a relatively high level of completely random noise. This would be irrelevant for DC/DC applications, as this noise would be completely suppressed by the low-frequency output filter. For envelope tracking, with almost no output filtering, this noise was unacceptable. It turned out that the source of this random behavior was an uncontrolled phase relationship between the command signal and sawtooth generators. To understand this, see Figure 6, where identical sinusoidal input leads to significantly different step patterns, illustrating how the peak of the sine wave relates to phase relationships of the sawtooth pattern. The underlying baseband component is nearly identical, but harmonic content cannot be filtered out by using a large LC filter, as this would kill the bandwidth.

As some of the harmonic content becomes now unpredictable, so too is its resulting impact on the RF signal. This makes a difference because only predictable (deterministic) voltage ripple can be compensated by digital pre-distortion (DPD), which is commonly used in today systems.

Figure 8: Deterministic PWM pattern achieved by synchronizing the counters with the command signal. All counters increment simultaneously by one step only when the command signal is decreased in a given clock period

This random component was completely eliminated by a simple modification of the overall PWM generator. Instead of having all sawtooth counters free running, we now made them enabled always and only when the input signal commands “step down” in the multilevel pattern (see Figure 8). In this way independent dynamics of the sawtooth generator were eliminated and this, in turn, eliminated random components of the multilevel pattern.

Another significant source of randomness in the stepped pattern came from different control-to-switching delays of various subconverters. See Figure 9 for an illustration of this mechanism.

Figure 9: Output voltage distortion due to uneven subconverter delay. Both patterns are created with the same PWM signal; the lower pattern is affected by one of the subconverters having its delay increased by 50 ns

Despite identical PWM patterns for each subconverter, the combined multilevel pattern may differ very significantly because of the differences in the control-to-output delay of individual subconverters. Analysis has shown that in order to make this phenomenon negligible, it is necessary to achieve a delay consistency of at least 1 ns. This includes variation from the PWM controller, gate driver, and power MOSFET. Variation due to the load or temperature is unimportant, as it affects all channels in an approximately identical way. This type of timing accuracy normally can be achieved with an equalization procedure during manufacturing, or via self-adjustment circuitry implemented in the FPGA directly.

In this case we were able to simply take advantage of the excellent speed and accuracy of Vishay’s SiP2204. The envelope tracking modulator based on this part had only 80 ps of RMS jitter at the output voltage due to an uneven subconverter delay. This is negligible noise, even with 40 MHz RF signal bandwidth.

An article describing efficiency improvements of a power supply must include some discussion on what was done to optimize the power stage. In this application, with the DC power being provided at virtually no loss and only a small fraction of the power being output at 5 MHz to 10MHz per phase, the optimization of the SiP2204 power stage (see Figure 10 for a block diagram) was vastly different from standard buck regulators operating below the 1 MHz frequency range.

Figure 10: Block diagram of the Si2204 quad power stage

Since the current levels were low, the on-resistance of the MOSFETs were in the 0.25 Ω to 0.5 Ω range, and the design focused on reducing the switching losses that dominate at these high frequencies. Figure 11 shows the efficiency of the SiP2204 operating at 5 MHz per phase from a 24 V input to 15 V output.


Figure 11: SiP2204 efficiency curve using the 4.7 µH IHLP-2525EZ-01, operating at 24 Vin to 15 Vout at 5 MHz per phase

Now in order to improve switching losses, the rise time of the high-side FET turn ON is designed to be extremely fast, in the order of 25 V/ns. These fast rise times result in a large spike on the switch node. By reducing the break-before-make (BBM) time, this spike can be reduced by inducing a small amount of shoot through. Usually shoot through is to be avoided, but the minor losses induced by allowing for a small amount of shoot through are outweighed by the efficiency improvements obtained by the fast dv/dt on the switch node rising. It also serves to reduce the ringing and allows the use of a 30 V MOSFET breakdown with an input voltage of 24 V.

At these high frequencies, propagation delays in the PWM input are detrimental to the performance of the power stage. Several innovative design techniques were used to reduce the PWM propagation delay to a mere 13 ns, which is specified as the delay from the PWM input to the switch node rising. This is a critical specification, because the switch node high-to-low transition, if slower, will only cause a PWM pulse width error that the controller can adjust by subtracting a fixed offset to the PWM duration.

To reduce the propagation delay, the following was done:

  1. The PWM interface uses a Schmidt trigger that has been redesigned for speed (higher peak current during transitions).
  2. The design avoides changing supply domains in going from logic to power, so there’s no need for level shifters (which are slow) on the path from PWM to the low-side gate.
  3. The low-side MOSFET driver’s strength was increased to ensure an extremely fast low-side MOSFET turn OFF time, thus allowing the reduction of the BBM time.
  4. The speed of the drivers was increased by eliminating the internal BBM.

Layout was also critical in getting the superb channel-to-channel matching accuracy achieved by the SiP2204.
 
Last but not least, the SiP2204 packs four high-performance switching power stages into one small package, allowing a very compact design of the whole 16-level converter to be achieved (see Figures 12 and 13). This not only results in the convenience of a small overall package, but also allows traces to be kept very short with minimum parasitic inductance and coupling, which is an absolute must for delivering current at tens of MHz.
           

Figure 12: 16-level envelope tracking modulator based on four SiP2204s (1.4 in x 3.4 in)

 

Figure 13: 16-level envelope tracking modulator, controller / cooling side, with a visible low-cost Cyclone FPGA used to implement a controller.
 
The technology of the 100 MHz regulation bandwidth voltage modulator described in this article has been patented and is available for licensing.


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