DSP-based system-on-chip targets hearing aids and hearing implant devices
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With five times the processing power of previous systems, the system-on-chip (SoC) provides built-in flexibility to support evolving algorithm, wireless and system-level needs.
The chip’s unique quad-core architecture is constructed of a 24-bit open-programmable CFX DSP core. Inclusion of the ARM Cortex-M3 processor supports wireless protocols and complements the DSP core with special error-correction and audio coding support. The system also features a HEAR configurable accelerator engine, dedicated for audio processing tasks, and a new filter engine which implements efficient time-domain filters. When combined with non-volatile memory and wireless transceivers, it forms a complete hardware platform.
Manufactured using 65nm process technology, the series integrates analogue front-end circuitry with an unmatched input dynamic range of 110 decibel (dB) that enables high sound precision and quality. A programmable Filter Engine supports an ultra-low delay audio path of 44μs for superior performance of features such as occlusion management. The addition of an integrated wireless controller, compatible with NFMI and RF wireless technologies, supports efficient data transfer to and from wireless transceivers.
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