Dolphin Design in France has launched an updated version of its Maestro power controller design block.
The conventional approach for the design of a power management unit (PMU) in a system-on-chip is to use a software-based solution to control the devices involved in power management. Software brings a highly flexible and configurable alternative for PMU implementation, but it requires an always-active CPU to manage the power schemes, with the penalty of hundreds of power-consuming CPU clock cycles and accesses to Flash memory.
Another approach used by design teams with more experience in power management is to adopt hardware solutions to enable low-latency control of their power devices with decreased power consumption. However, designing full custom logic for power control requires an in-depth expertise in power management and drastically increases the design and verification cycle time. In addition, a full-custom PMU tailored for a given circuit is hardly portable and scalable to another product, even for low or mid-complexity SoC.
The latest version of the Maestro Ip block combines the configurability of a software PMU together with the lowest power consumption of a hardware PMU.
The block supports dual operation modes, from CPU-less operation for low-power and low latency control of power devices to a flexible SW operation mode with a standard 32bit APB interface that enables on-the-fly execution of software-based power sequences. This is possible using an embedded sequencer for autonomous control of power mode transitions, including boot-up and wake-up sequences where CPU is off. An event-based architecture to trigger any power sequence (up to 16 pre-programmed HW events) while a built in 10MHz oscillator enables fast wake-up when RTC clocks are shutdown.
All of this provides fine-grain control of power devices in the design such as regulators, clock generators with standard p-channel interface, enabling smooth support of both IP from Dolphin Design or third party IP providers
This now works with Dolphin’s PowerStudio compiler to speed-up the design of a highly scalable power controller. The tool includes Power State Table and Power Mode Changes GUI for fast configuration, a gate count & transition time calculator as well as automated generation of Maestro RTL configuration and of UPF test-bench for PMU in-context verification.
The design is currently being used to enable multiple customer tape-outs in various silicon technology nodes, including FD-SOI and bulk technologies.
- IMAGINATION AIMS WIFI6 IP AT LOW POWER IOT
- MULTIPHASE CONTROLLERS AND SMART POWER FOR 1000A AI LOADS
- SEVEN CHANNEL POWER MANAGEMENT CHIP SUPPLIES 0.6V FOR FUTURE PROCESSORS
Other articles on eeNews Power