DC/DC converter PCB layout, Part 2

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By eeNews Europe

High efficiency, high density and low production costs drive the continual development of DC/DC converters for an increasingly wide range of power supply applications for automotive, industrial, personal electronics and communications markets. To achieve these design targets, a compact yet innovative printed circuit board (PCB) layout design of the switching converter goes a long way in the push for a smaller footprint solution. The PCB layout itself is typically a multi-objective discipline, as it directly influences electrical, mechanical, thermal and electromagnetic behaviors.

Part 1 of this three-part series [1] focused on power converter PCB design and related considerations. The four-switch buck-boost converter topology offers a convenient platform to study PCB layout, as you can easily extrapolate the analysis to other topologies. Steps 1 and 2 (covered in part 1) discussed multilayer PCB stackup and the critical current loops and voltage nodes of the switching converter. Here in part 2, I will explore step 3, the power component placement for optimal switching regulator performance, looking also at power stage thermal design and electromagnetic interference (EMI) considerations. Step 4 delves into control IC and small-signal component floor planning and location.

Step 3: Power-stage component placement

Based on the high di/dt current loop identification detailed in step 2 (part 1), thoughtful and strategic placement of the power stage components is essential. With increasing switching speeds and lower package parasitics, the bottleneck in power MOSFET switching performance is shifting from silicon to the commutating loop parasitic impedance [2]. Using the synchronous buck-boost topology example layout in reference 3, the screen capture in Figure 1 illustrates placement of power MOSFETs, wide aspect ratio footprint current shunt, and input and output ceramic capacitors on the PCB’s top layer.


Figure 1: To the left is the PCB top layer with power-stage component layout showing tight AC current-loop conduction paths. To the right is a schematic of the 4-switch buck-boost power train, including power MOSFETs, shunt, inductor, and input and output capacitors.
The lower-profile MOSFETs (3 mm x 3 mm) and ceramic capacitors (1210 footprint) are purposely located on the top side of the PCB. Meanwhile, the taller components (inductor and bulk capacitors) are on the bottom side. Input capacitors are located close to buck-leg MOSFETs. Similarly, output capacitors are located adjacent to boost-leg devices, resulting in a tight, symmetric layout for both switching legs. Note that the shunt resistor enlarges the area of both switching loops. A shunt resistor with a wide aspect ratio (1225 footprint) and a shorter conduction path provides low inductance as well as reduced lengths of power loops 1 and 2, denoted by the while borders in Figure 1.

H-field self-cancellation

Power-loop parasitic inductance increases MOSFET switching loss and peak drain-to-source voltage spikes. It also exacerbates switch-node voltage ringing, affecting broadband EMI in the 50- to 300-MHz range. While minimizing the physical size of the loop by paying attention to component placement is important to reduce loop inductance, noise coupling also depends on field distribution/orientation, making the design of a PCB’s inner layers noteworthy.

As discussed in references 4 to 8, a passive shield layer is established by placing a ground plane as close as possible to the switching loop by using a minimum dielectric thickness. The horizontal current flow on the top layer sets up a vertical flux pattern. The resulting magnetic field induces a current, opposite in direction to the power loop, in the shield layer. By Lenz’s law, the current in the shield layer generates a magnetic field to counteract the original power loop’s magnetic field. The result is an H-field self-cancellation that amounts to lower parasitic inductance, reduced switch-node voltage overshoot, and enhanced suppression of EMI [7]. Having an uninterrupted, continuous shield plane on layer 2 underneath and at closest proximity to the power loop offers the best performance. Narrow intralayer spacing is specified in the PCB stackup, using a 6-mil core dielectric for example.

Power stage thermal design
While a high-density layout is generally positive for conversion efficiency as conduction voltage drops are reduced, it may create a thermal performance bottleneck. A push-pull dynamic is in play here: The same power dissipation in a smaller footprint becomes unacceptable. To maximize thermal performance in convective airflow, place the MOSFETs on the top side of the PCB. In this configuration airflow is not shadowed by taller components such as the inductor and electrolytic capacitors. Depending on the application, it is possible to locate the inductor on the bottom side of the PCB, since it may impede heat transfer if placed on the top. Owing to its size, the inductor intrinsically acts as its own heat sink.
With respect to the 4-switch buck-boost converter being discussed here, the low-side MOSFET of the non-switching leg is held off in pure buck or boost modes. This offsets the adjacent high-side device that conducts the inductor current continuously with concomitant power loss. Conversely, with deep buck or boost operation (that is, low buck or high boost duty cycle), the switching-leg MOSFET selection tilts toward managing low-side power loss and temperature rise. As shown in Figure 1, the high-side MOSFETs’ drains are attached with short connections to the VIN or VOUT power terminals through heat-spreading copper planes. Their drain tabs are also joined by numerous thermal vias to corresponding copper planes on the bottom layer. Thus, the high-side MOSFETs are adequately heat-sinked.
The thermal challenge of this design is the low-side MOSFETs whose drain tabs are attached to switch-node copper polygons with via connections to the inductor below. Now, the important variable here is switch-node copper area. Provisioning for low EMI places an emphasis on a minimal switch-node copper area to reduce capacitive coupling related to high dv/dt switch-node voltage transitions [8] and reduce e-field radiated emissions. Nevertheless, a larger switch-node copper area assists in thermal spreading related to dissipation from the inductor and low-side MOSFETs. A PCB layout for larger 5-mm x 6-mm footprint MOSFETs with lower thermal impedance is achieved with a relatively minor edit to the layout in Figure 1.

Step 4: Control IC location and bottom side PCB layout

If the control IC has integrated gate drivers, it becomes imperative to locate the IC as close as possible to the power MOSFETs. Then, the gate driver traces that run from the IC to the MOSFETs are kept as short and direct as possible to minimize parasitic gate inductance.
On a single-sided PCB design, the only option is to place the control IC on the top (component) side of the PCB close to the power devices. However, achieving short gate drive connections is often complicated by the power stage layout (particularly if more than two MOSFETs are required, as in the 4-switch buck-boost, multi-phase buck or boost, and full-bridge converters). The necessary signal-level components, connecting traces and vias that typically surround the IC also make its placement more difficult. It is often advantageous in a two-sided layout to place the IC on the bottom (solder) side of the PCB. This helps gate drive circuit performance and shields sensitive analog circuits from switching noise and high operating temperatures characteristic of power devices. Figure 2 illustrates this strategy for the bottom side layout

Figure 2: Bottom layer of PCB (layer 6) viewed from below. Small-signal components surrounding the control IC are located on a separate ground (GND) island.
Higher-profile electrolytic capacitors are placed on the bottom side for three reasons. First, they are of similar height to the banana connections for the power terminals in this design and, thus, impose no height penalty. Second, they conduct low- to mid-frequency current harmonics [9], making very close placement to the MOSFETs superfluous. Third, airflow shadowing from the electrolytic capacitors is largely inconsequential, as the lower-profile, heat-dissipating MOSFETs are sited on the top side of the PCB.
The noise-sensitive small-signal components for the compensation network, feedback resistors, frequency set resistor, soft-start capacitor and current sense filter are located close to their respective pins (COMP, FB, RT, SS, CS, CSG) and have a dedicated analog ground (AGND) plane that ties to the IC’s AGND pin. Power ground (PGND) connects to the exposed pad of the IC with thermal vias to inner ground planes. PGND connects to AGND locally there as well for single-point grounding.

Reducing converter losses is an essential requirement to enable compact realization and a flexible deployment of the converter within the intended system. Thoughtful placement and layout of the power stage components in a PCB design enable better switching performance, higher efficiency, lower operating temperatures and reduced broadband EMI for easier regulatory compliance [8].
Stay tuned for part 3 of this series, when I will delve into the detail of routing critical traces for gate drives, output voltage feedback and current sense, and finally ground management, in tandem with a polygon plane design of the outer and inner layers of the multilayer PCB.

  1. T. Hegarty. “DC/DC converter PCB layout, Part 1
  2. LM5175EVM-HD 400-kHz buck-boost converter design   
  3. T. Meade et al. “Parasitic inductance effect on switching losses for a high frequency DC/DC converter.” APEC 2008, pp. 3-9
  4. Bhargava et al. “DC/DC buck converter EMI reduction using PCB layout modification.” IEEE Transactions on EMC, August 2011, pp. 806-813
  5. Reusch et al. “Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter.” APEC 2013, pp. 649-655
  6. K.W. Kam et al. “EMC guideline for synchronous buck converter design.” 2009 IEEE International Symposium on EMC, pp. 47-52
  7. M. Montrose. “Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers,” second edition. IEEE Press, 2000
  8. Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x.” TI application note (SNVA721A), September 2014
  9. T. Hegarty. “Paralleling electrolytic and ceramic capacitors perks up POL transient response.” How2Power, March 2011

About the author

Timothy Hegarty is a Systems and Applications Engineer in the Power Products Solutions Unit at Texas Instruments, Phoenix, AZ. He received the bachelor’s and master’s degrees in Electrical Engineering from University College Cork, Ireland in 1995 and 1997, respectively. Prior to Texas Instruments, he worked for National Semiconductor, Artesyn Technologies, and Melcher. His areas of interest are high-efficiency isolated and non-isolated converters, wide input voltage range PWM regulators and controllers, resonant converters, renewable energy systems, and system-level simulation of same. He is a member of the IEEE Power Electronics Society.


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