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DC/DC converter PCB layout, Part 1

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By eeNews Europe

Fundamental to careful system design of any DC/DC power converter is a well-planned and carefully executed printed circuit board (PCB) layout. An optimized layout leads to better performance, lower cost and faster time-to-market. Additionally, it can constitute a competitive advantage for the end equipment user owing to higher reliability (lower component temperature), easier regulatory compliance (lower conducted and radiated emissions), and improved space utilization (reduced solution volume and footprint).

A primary objective of this three-part article series is to look closely at PCB layout design, knowing that it represents a critical piece of the power converter puzzle. These articles also offer clear guidance on factors related specifically to PCB design to achieve low noise converter implementations. Using a four-switch synchronous buck-boost DC/DC converter as a case study, PCB layout considerations for fast-switching, high-current applications are highlighted using a step-by-step process. The real purpose here is a practical one. PCB layout, one of the thorniest and most menacing topics for a power supply engineer, can make or break a real design.

Four-switch buck-boost converter review
 
Let’s digress for a moment to introduce the four-switch (non-inverting) synchronous buck-boost topology. This circuit is an excellent example to study DC/DC converter PCB layout. It has  numerous applications including industrial computing, LED lighting, RF power amplification, and USB power delivery [1]. The most compelling feature of this particular buck-boost implementation is that buck, boost, and buck-boost transition modes are engaged as needed to achieve high efficiency across wide and overlapping input and output voltage ranges.

One common application scenario is deriving a tightly-regulated 12V rail from an automotive battery source. Even if the battery’s DC voltage varies from 9V to 16V, transients arise from start/stop, cold crank or load dump. [2]
The voltage during such events can dip as low as 3V or spike to 42V, sometimes even higher. To meet these requirements, the schematic in Figure 1 illustrates components for the power stage and controller, including integrated gate drivers, bias supply current sensing, output voltage feedback, loop compensation, programmable undervoltage lockout (UVLO), and dither option for lower noise signature.
 

Figure 1: 4-switch synchronous buck-boost converter schematic.
 
The four power MOSFETs in Figure 1 are arranged as buck and boost legs in an H-bridge configuration, with switch nodes SW1 and SW2 connected by inductor Lf. Conventional synchronous buck or boost operation occurs when the input voltage lies suitably above or below the output voltage, respectively. Meanwhile, the high-side MOSFET of the opposite, non-switching leg conducts as a pass device. More importantly, as the input voltage approaches the output voltage, the buck or boost leg that is switching reaches an anticipated threshold. This triggers a changeover to buck-boost transition mode, in this case a hybrid of buck and boost modes interleaved as required for an aggregate buck-boost effect [3].

Power converter PCB design flow
 
PCB design for high-current, fast-switching converters demands more caution than ordinary PCBs, since the voltage drops caused by parasitic impedances become really significant in high-current and high slew rate conditions [4]. Even though the topic of PCB design is fraught with subjectivity, the best practices for a PCB design also facilitate high-density and small-solution size. What is equally relevant is that many of these practices align with safeguards to help curtail electromagnetic interference (EMI), and ease regulatory compliance for emissions and immunity specifications [5].
 
Let’s review a design flow for a 400 kHz 4-switch buck-boost converter that delivers a 12-V output rated at 6A derived from an input source ranging from 5.5V to 42V [6]. The concepts outlined here are general design guidelines for buck or boost circuits, both synchronous and non-synchronous, with similar design constraints.

Following several essential steps, the PCB design flows from planning the PCB stackup configuration, identification of the critical converter switching loops, power stage component floor planning, connection routing, to polygon plane design of outer and inner layers of the multi-layer PCB.

Step 1: PCB stackup design

 
A fundamental understanding of the PCB structure is quite important, even if design of the stackup is delegated to the PCB manufacturer. Defining a multi-layer PCB stackup has numerous advantages over a single- or double-sided PCB. The multi-layer option supports higher current capability and lower conduction drop, better thermal spreading, and substantially improved EMI performance. The availability of a ground plane on layer 2 closely couples to the high-current switching loops that normally reside on the top layer and helps to reduce parasitic inductance. As will be discussed in more detail in Part 2, the importance of a continuous and solid image plane on layer 2 cannot be overstated [5].


Figure 2: Stackup configuration for a six-layer FR-4 PCB with 2-oz copper in all layers, and a 62 mil finished thickness.

The PCB stackup diagram in Figure 2 conveys the pertinent information for the fabrication of the PCB. This diagram includes electrical layers and associated copper weight, substrate (dielectric) layers classified as core and prepreg, solder mask, via drill types, and relevant layer thicknesses that aggregate to the total PCB height. A core of given height is supplied with copper foil bonded on both sides. Likewise, various plies of resin pre-impregnated fiberglass, or prepreg, are combined to achieve the desired prepreg thickness. The stackup option shown here is termed layer pairs and refers to the order of the core and prepreg layers throughout the layer stack [6]. Figure 2 shows top, middle and bottom cores sandwiched by two layers of prepreg. Other stackup styles commonly supported by PCB manufacturers are shown in Figure 3. The stackup is particularly important if blind or buried vias are planned, as the drill pairs are defined to suit the layer stackup style.

 

Figure 3: Alternative layer stacks for six-layer PCB: internal layer pairs (a), and build-up (b).
 
One industry-standard of laminated thickness specification is 62 mils (1.6 mm). 1 ounce (oz) copper refers to a weight of 1oz/ft2 and corresponds to a foil height of 1.4 mils (0.035 mm). Thus, trace resistance is derived based on the trace length and width, and the resistivity of copper at the applicable operating temperature.

Step 2: Identifying high slew rate current loops

 
With an eye towards understanding the layout-induced parasitic inductances that cause excessive noise, overshoot, ringing and ground bounce, it is imperative to identify the high slew rate current loops, or hot loops, from the converter schematic. As illustrated in Figure 4, loops 1 and 2 (shaded in red) are classified as high-frequency switching power loops for the buck and boost legs, respectively. During a MOSFET switching event where the slew rate of the commutating current can easily exceed 5 A/ns, just 2 nH of parasitic inductance results in a voltage spike of 10V. Insofar as the rectangular current waveforms in the identified power loops are rich in harmonic content, a severe threat of magnetic field coupling and radiated EMI exists. Clearly, it is vital to minimize the effective loop length and enclosed area in loops 1 and 2. This reduces parasitic inductance, enables magnetic field self-cancellation [4], and reduces the radiated energy emanating from what are effectively loop antenna structures.

Figure 4: Buck-boost converter schematic with critical loops categorized for high slew rate currents. Power loops 1 and 2 are for the buck and boost legs, respectively. Loops 3, 4, 5 and 6 denote MOSFET gate driver loops during turn-on and turn-off switching transitions.
 
In contrast, the current flowing in the filter inductor is largely DC with a superimposed triangular ripple. The rate of change of current is inherently limited by the inductance, and any parasitic inductive component contributed by the series connections is essentially benign.
 
Loops 3 – 6 in Figure 4 are classified as gate loops for the buck and boost legs. Specifically, loops 3 and 4 (outlined in green) represent the high-side MOSFETs’ gate driver circuits supplied by their respective bootstrap capacitors. Likewise, loops 5 and 6 (blue) designate the low-side MOSFETs’ gate drivers supplied by VCC. The turn-on and turn-off current paths, denoted by solid and dashed lines, respectively, are delineated in each case. To charge and discharge the MOSFETs’ effective gate capacitance during turn-on and turn-off transitions, high slew rate current up to 5A peak – depending on gate driver strength, series gate resistance and inductance, and MOSFET capacitance – flows briefly in each gate loop.
 
The low-side gate driver loops’ enclosed areas are minimized by placing the VCC decoupling capacitor very close to the VCC and PGND pins. Similarly, the high-side gate driver loops’ enclosed areas are diminished by positioning the bootstrap capacitors close to their respective SW and BOOT pins [7]. The gate driver traces from the controller to the MOSFETs are kept as short and direct as possible.
 
Summary

A four-switch buck-boost topology facilitates the discussion of power converter PCB layout, starting with an understanding of the required PCB stackup and identifying the key converter switching loops from the schematic. Diligently minimizing these loop areas during layout of the PCB is imperative to abate parasitic inductance, magnetic field coupling, and radiated EMI.

Stay tuned for Parts 2 and 3 of this article where I delve into the detail of power stage component floor-planning, thermal design considerations, strategic placement of the PWM controller, routing of critical traces for gate drives, current sense and feedback, small-signal component placement and routing, and finally polygon plane design of the multi-layer PCB.
 
References

  1. Wide VIN power solutions
  2. Automotive wide VIN DC/DC brochure
  3. LM5175EVM-HD 400 kHz buck-boost controller high density EVM
  4. Using a circuit-driven approach to teach printed-circuit board (PCB) layout techniques for switching power supply circuits, Rincón-Mora et al
  5. EMI and layout fundamentals for switched-mode circuits, R.W. Erickson
  6. Layer stack manager
  7. Layout considerations for LMG5200 GaN Power Stage, Application Note (SNVA729), Texas Instruments, March 2015

About the author

Timothy Hegarty is a Systems and Applications Engineer in the Power Products Solutions Unit at Texas Instruments, Phoenix, AZ. He received the bachelor’s and master’s degrees in Electrical Engineering from University College Cork, Ireland in 1995 and 1997, respectively. Prior to Texas Instruments, he worked for National Semiconductor, Artesyn Technologies, and Melcher. His areas of interest are high-efficiency isolated and non-isolated converters, wide input voltage range PWM regulators and controllers, resonant converters, renewable energy systems, and system-level simulation of same. He is a member of the IEEE Power Electronics Society.


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