Challenges in power management architectures with internal regulation

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By eeNews Europe

Modern day SoCs are meant to support a number of functions in the field. This requires the SoC to have different IPs, peripherals etc. These subsystems in the design work on different voltage levels and are power hungry, also having different current requirements. Amongst these voltages, some are externally supplied, while others are internally generated.

For the internally generated voltages these SoCs may have more than one regulator catering to different needs e.g. high bandwidth, low drive and low bandwidth, high drive, but all regulating a single voltage supply (let this be the voltage for the digital IPs). When many of these digital functionalities get activated at the same time there are chances of current surges being seen on this internally regulated voltage supply. As standalone entities most of these regulators are flawless but when integrated into the SoC it is particularly important to see that this happens seamlessly.

Some critical issues that should be taken care of during integration are as follows:

a) The enabling of regulators from the Digital wrappers during the power-up phase of the SoC depending on the use case of regulators and its features.

b) The individual regulation levels of the regulators which ensure that the usage of the regulators is optimum and the system is immune to any dynamic current consumption profile changes.

c) Handling the disable of regulators to avoid spikes on the current profile of supply during shut down of the device.

d) Regulators should support bypass feature for Test mode where an external control on all the supplies is needed.

Let us take up each of these issues in detail.

a) Power-up Phase

1) Masking of data coming from the digital domain

Consider the case when these regulators generate the supply on which the digital logic in the SoC works. Since this supply is building up in the power-up phase of the system, any signal coming from the digital domain is at a floating value, which can be at any level.

Hence this value has to be rejected until at least the digital supply in the system reaches a level after which the digital logic can be trusted. This level, of which the inputs coming from the digital domain should be masked, is the POR_REGULATED_SUPPLY which is about 0.7V (i.e. close to the threshold level of active devices).

  • Any logic which the system needs until this level is attained has to be safe-stated to ground level.
  • This safe-stating is removed only when the POR_REGULATED_SUPPLY is reached.
  • If this is not taken care of, then the system can be stuck in a loop where it will never come out of the Reset state.

2) Digital Wrapper of the regulators

The one problem that often arises in multi-regulated systems is related to the reuse of the logic, residing in the digital wrapper, for power down of the regulators. In general this skips the attention of most chip design and integration verification engineers that though the design of these regulators, namely the MAIN and AUXILIARY regulator, is similar but the functions that they serve in the SoC are different.

How and when these regulators come out of their power down state w.r.t. each other is very important.

    As the work of the MAIN regulator is to build up the internally regulated voltage and to carry the complete load of the device, it should always be ON (i.e. it should start as soon as the POR of the PMU_HV_SUPPLY is released).
    The SUPPORTING regulator comes alive when the current load on the MAIN regulator is likely to increase and not by itself bring up the regulated voltage. It will only support the MAIN regulator in regulating the supply during sharp current transients.
3) Inrush Current in Regulators

The main regulator should follow a slow ramp to generate the regulated voltage supply. The SUPPORTING regulator does not follow a ramp but a constant voltage value at which it is required to maintain the supply.

There is a reason why the MAIN regulator follows a slow ramp (the ramp rate being the decisive factor) and not a constant voltage or fast transitioning voltage. This is because of following reasons:

  • If this not be the case then a huge inrush current (Shown in Figure 1) will be observed due to the sudden charging of the capacitive loads at the internally regulated voltage node.
  • In addition to this, the regulated supply also has to follow the ESD rules, as the ESD trigger circuit sitting inside the supply PADs can issue a false ESD trigger, if the ramp rate of this supply is faster than the ESD specifications.


Figure 1: The Ramp rate vs. Inrush Current in LDO

4) Issue seen with the improper enable logic of the regulators and the solution  suggested

One classic issue which is observed and is sometimes left unattended is, when exactly the SUPPORTING regulator is switched ON. Let us consider one such problematic case and how exactly this can be rectified.

The main regulator is switched ON as soon as the external voltage supply (which is the supply required by the regulator to function) crosses its POR (Power On Reset) level POR_EXTERNAL_SUPPLY. The main regulator then begins to build the voltage supply, slowly ramping it up.

The logic of the pd (power down) of the SUPPORTING regulator may be such that the SUPPORTING regulator is turned ON when this regulated voltage supply reaches its POR level, POR_REGULATED_SUPPLY (the MAIN regulator still ramping it up). This minimum voltage level at which the SUPPORTING regulator comes out of its power down state is what is problematic. This is because as soon as the SUPPORTING regulator comes out of its power down state it follows the constant regulated voltage supply value and takes its own output to that level.

Since the output of the two regulators are shorted (as shown in Figure 2) so the SUPPORTING regulator ends up pulling the regulated voltage value to the final static value from its POR value in a few nanoseconds time interval which poses serious ESD threats to the system (Refer Fig3(a)).

Figure 2: Integration of Main and Auxiliary Regulator

Figure 3 (a): Issue in vdd_lv ramp when the PD of Supporting Regulator is gated with POR of vdd_lv

The solution suggested to this problem here is simple and easy to implement.

  • The power down of the SUPPORTING regulator should be gated with the reset state signal of the SoC.
  • By doing this the Supporting regulator is not able to come alive until the System is out of the Reset state (Refer Fig3 (b)) and the main regulator is up and stable.
  • This ensures that, when the System encounters any current surges due to the digital IPs (which are in power down condition when the system is in Reset) the Supporting regulator is alive and ready to support the MAIN regulator as desired.

Figure 3 (b): Solution to the issue in Fig3 (a) by gating the pd of Supporting Regulator with Reset_b

b) Regulation level of the individual regulators

1) Regulation level of the MAIN and AUXILIARY regulator wrt each other

The next issue with multi-regulated systems is the regulation level of the individual regulators and how the overall system is one that gives maximum stability in voltage level and is seasoned to any dynamic current changes in the system.

The integration of these regulators in the SoC is done such that the regulation level of the MAIN regulator is above the regulation level of the AUXILIARY regulator (by approximately 100mV or so at least). This is because when the stabilization of the internally generated voltage is ensured by the MAIN regulator then we don’t want the AUXILIARY regulator to be ON.

When this voltage begins to fall in value and reaches the regulation level of the AUXILIARY regulator it is then that the AUXILIARY or SUPPORTING regulator turns ON. And since its bandwidth (time taken by the regulators to respond to any transients) is much higher as compared to the MAIN regulator, the voltage level stabilization takes place quickly thus preventing the system from hitting low voltage detection (LVD).

The SUPPORTING regulator thus ensures that the response time, in case of current surges, will be really low. This scheme of the SUPPORTING regulator is useful during increase of the system clock frequency (as high as 10x) where chances of hitting LVD is high.

2) Reason behind the difference in Regulation level

The current consumption of the AUXILIARY regulator in itself is high, (since it is designed such that it has a high bandwidth). This can overall increase the current consumption of the chip thereby leading to higher power dissipation. Therefore, the AUXILIARY regulator should regulate the voltage level only when this voltage begins to fall due to some dynamic current consumption changes in the digital domain.

 Figure 4 (a): Main Regulator alone unable to handle the instability due to increase in frequency causing LVD conditions

Figure 4 (b): Auxiliary Regulator supporting Main Regulator to avoid LVD conditions during increase in system frequency

3) Common/Uncommon Bandgap References for the regulators: A comparison

Further, the reference that goes as the input to the regulators should be taken care of. This reference is the bandgap voltage reference which is the absolute internal voltage reference for the system.

To understand the issue better let us first consider that there are two different bandgap voltage references whose outputs go to each of these regulators. This may have the following issues:

  • If due to any intrachip Process-Voltage-Temperature (PVT) variations, the reference value generated by one goes above/below the other one, this will result in changing the regulation levels of the two regulators.
  • This in turn may end up spoiling the intention of keeping the regulation level of AUXILIARY regulator below the MAIN regulator.

So what needs to be taken care of is that the bandgap reference, going as an input to both these regulators, must be the same. This ensures that any changes in the intrachip PVT conditions do not affect the regulation levels of the two regulators in internal regulation mode.

c) Power down Phase

The next important consideration for multi-regulated systems is the behavior in the power down phase. When the system is in its Power down phase then the internally regulated voltage supply begins to fall (as shown in Figure 5).

This may be the scenario during some kind of power gating of a domain in the system which uses the internally regulated supply.

  • When doing so the AUXILIARY regulator misunderstands the scenario to be of an accidental power down and tries to bring up the supply as soon as its regulation level is reached.
  • Since the current consumption in the AUXILIARY regulator is high, it ends up consuming a lot of current which is seen as a current spike in the system.

To avoid any such case it needs to be looked into that the AUXILIARY regulator should be explicitly turned OFF before the system is powered down for any reason.


Figure 5: Power Down of the SoC causing the POR_regulated_supply to get asserted again thus making the system go into RESET phase.

d) Test Mode (Regulators with External/Internal Ballast)

1) Requirements of Test mode

When the SoC is in the Test mode, then all the supplies are externally supplied. This is because, to test many components in the SoC, the supplies need to be varied over a range of voltages for which it is mandatory that the internal regulator can be bypassed and there be an external control for the supplies. Generally the MAIN regulator is seen to have an external ballast because it has a high current load supporting feature, and the AUXILIARY regulator has an internal ballast.

2) Problematic scenario in Test mode and the ideal approach

When in the test mode, the external ballast is always taken care of, it is removed so that the MAIN regulator is not able to bring up the internally generated supply. But it is often forgotten that there is another regulator, the AUXILIARY regulator, which has an internal ballast and so it needs to be disabled explicitly.

If not disabled, then varying the voltage (which is now being both externally supplied and internally regulated by the AUXILIARY regulator) will not be possible because every time the external voltage level will fall below the regulation level of the AUXILIARY regulator it will try to bring it up, and the very basic motive behind having external control of the supplies in test mode will not be fulfilled.


Hence the reason why SoCs these days have more than one regulator is straightforward. It is making an SoC that has a multi-regulator subsystem which is robust in every way. The MAIN regulator is so designed that it can support more load and the SUPPORTING regulator is present so that it can ensure fast responses, is able to handle sharp transients and adds stability. Thus the two regulators go hand in hand. One handles load while the other supports transients. There are integration issues associated with it that demand one’s thorough attention. It is our job as designers to make sure that the integration is correct.


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